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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(396003)(39850400004)(346002)(136003)(376002)(46966006)(36840700001)(82310400003)(7696005)(36860700001)(9686003)(70586007)(55016002)(47076005)(5660300002)(81166007)(33656002)(83380400001)(356005)(336012)(8676002)(52536014)(6506007)(186003)(54906003)(82740400003)(4326008)(8936002)(53546011)(70206006)(26005)(2906002)(110136005)(478600001)(316002)(450100002)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2021 03:41:22.3101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8323ac19-64f6-4ed5-77e8-08d93f66c1f9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB2112 Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: add logic of processing continuous DD bits for Arm X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Wednesday, June 30, 2021 9:15 AM > To: Joyce Kong ; beilei.xing@intel.com; > qi.z.zhang@intel.com; Ruifeng Wang ; > bruce.richardson@intel.com; helin.zhang@intel.com > Cc: dev@dpdk.org; stable@dpdk.org; nd ; Honnappa > Nagarahalli ; nd > Subject: RE: [PATCH v2] net/i40e: add logic of processing continuous DD b= its > for Arm >=20 > > > > > For Arm platforms, reading descs can get re-ordered, then the status > > of DD bits will be discontinuous, so add the logic to only process > > continuous descs by checking DD bits. > > > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > Cc: stable@dpdk.org > > > > Signed-off-by: Joyce Kong > > Reviewed-by: Ruifeng Wang > > --- > > drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++++---- > > 1 file changed, 15 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_rxtx.c > > b/drivers/net/i40e/i40e_rxtx.c index 6c58decec..86e2f083e 100644 > > --- a/drivers/net/i40e/i40e_rxtx.c > > +++ b/drivers/net/i40e/i40e_rxtx.c > > @@ -452,7 +452,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > > uint16_t pkt_len; > > uint64_t qword1; > > uint32_t rx_status; > > - int32_t s[I40E_LOOK_AHEAD], nb_dd; > > + int32_t s[I40E_LOOK_AHEAD], var, nb_dd; > > int32_t i, j, nb_rx =3D 0; > > uint64_t pkt_flags; > > uint32_t *ptype_tbl =3D rxq->vsi->adapter->ptype_tbl; @@ -482,11 > > +482,22 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > > I40E_RXD_QW1_STATUS_SHIFT; > > } > > > > - rte_smp_rmb(); > > + /* This barrier is to order loads of different words in the > > descriptor */ > > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > I think this should go into a separate commit as the following change is > unrelated. Will separate the two changes in v3. >=20 > > > > /* Compute how many status bits were set */ > > - for (j =3D 0, nb_dd =3D 0; j < I40E_LOOK_AHEAD; j++) > > - nb_dd +=3D s[j] & (1 << > > I40E_RX_DESC_STATUS_DD_SHIFT); > > + for (j =3D 0, nb_dd =3D 0; j < I40E_LOOK_AHEAD; j++) { > > + var =3D s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); > > #ifdef > > +RTE_ARCH_ARM > > + /* For Arm platforms, only compute continuous > > status bits */ > > + if (var) > > + nb_dd +=3D 1; > > + else > > + break; > > +#else > > + nb_dd +=3D var; > > +#endif > > + } > > > > nb_rx +=3D nb_dd; > > > > -- > > 2.17.1