回复: [PATCH v5 2/2] eal: add power mgmt support on Arm

[Feifei Wang <Feifei.Wang2@arm.com>]

> -----邮件原件-----
> 发件人: Stephen Hemminger <stephen@networkplumber.org>
> 发送时间: Saturday, February 18, 2023 12:23 AM
> 收件人: Feifei Wang <Feifei.Wang2@arm.com>
> 抄送: Ruifeng Wang <Ruifeng.Wang@arm.com>; dev@dpdk.org; nd
> <nd@arm.com>; David Hunt <david.hunt@intel.com>
> 主题: Re: [PATCH v5 2/2] eal: add power mgmt support on Arm
> 
> On Wed, 14 Dec 2022 16:14:30 +0800
> Feifei Wang <feifei.wang2@arm.com> wrote:
> 
> > +__check_val_size(const uint8_t sz)
> > +{
> > +	switch (sz) {
> > +	case sizeof(uint8_t):  /* fall-through */
> > +	case sizeof(uint16_t): /* fall-through */
> > +	case sizeof(uint32_t): /* fall-through */
> > +	case sizeof(uint64_t): /* fall-through */
> > +		return 0;
> > +	default:
> > +		/* unexpected size */
> > +		return -1;
> > +	}
> > +}
> > +#endif
> 
> One simplification would be to get rid of this function and just check for
> unexpected size in the switch statement in rte_power_monitor().


Thanks for the comments.

__check_val_size API is following intel path. And agree with your comments, 
for arm path, it is unnecessary.

Thus I will delete __check_val_size and simplify the code.

Best Regards
Feifei
> 
> > +	switch (pmc->size) {
> > +	case sizeof(uint8_t):
> > +		__RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > +		__RTE_ARM_WFE()
> > +		break;
> > +	case sizeof(uint16_t):
> > +		__RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > +		__RTE_ARM_WFE()
> > +		break;
> > +	case sizeof(uint32_t):
> > +		__RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > +		__RTE_ARM_WFE()
> > +		break;
> > +	case sizeof(uint64_t):
> > +		__RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value,
> __ATOMIC_RELAXED);
> > +		__RTE_ARM_WFE()
> 
> 	default:
> 		return -1; /* unexpected size */
> > +	}