From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 48DCC8E56 for ; Fri, 25 Sep 2015 13:48:08 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 25 Sep 2015 04:47:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,586,1437462000"; d="scan'208";a="568284345" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by FMSMGA003.fm.intel.com with ESMTP; 25 Sep 2015 04:47:49 -0700 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.168]) by IRSMSX101.ger.corp.intel.com ([169.254.1.139]) with mapi id 14.03.0248.002; Fri, 25 Sep 2015 12:47:48 +0100 From: "Mcnamara, John" To: Zoltan Kiss , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] ixgbe: prefetch cacheline after pointer becomes valid Thread-Index: AQHQ9yjB0u2J8igrZ0GFKpyLuHNAsJ5NITHA Date: Fri, 25 Sep 2015 11:47:47 +0000 Message-ID: References: <1443140606-18241-1-git-send-email-zoltan.kiss@linaro.org> In-Reply-To: <1443140606-18241-1-git-send-email-zoltan.kiss@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] ixgbe: prefetch cacheline after pointer becomes valid X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Sep 2015 11:48:08 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zoltan Kiss > Sent: Friday, September 25, 2015 1:23 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] ixgbe: prefetch cacheline after pointer > becomes valid >=20 > + if (split_packet) { > + rte_prefetch0(&rx_pkts[pos]->cacheline1); > + rte_prefetch0(&rx_pkts[pos + 1]->cacheline1); > + rte_prefetch0(&rx_pkts[pos + 2]->cacheline1); > + rte_prefetch0(&rx_pkts[pos + 3]->cacheline1); > + } > + > /* A* mask out 0~3 bits RSS type */ > descs[3] =3D _mm_and_si128(descs0[3], desc_mask); > descs[2] =3D _mm_and_si128(descs0[2], desc_mask); Hi, This patch doesn't apply cleanly. It looks like all the tabs have been repl= aced with spaces. John.