From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 9373E1094 for ; Sun, 2 Jul 2017 21:10:07 +0200 (CEST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Jul 2017 12:10:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,299,1496127600"; d="scan'208";a="121525110" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga005.fm.intel.com with ESMTP; 02 Jul 2017 12:10:04 -0700 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.26]) by irsmsx110.ger.corp.intel.com ([169.254.15.126]) with mapi id 14.03.0319.002; Sun, 2 Jul 2017 20:10:03 +0100 From: "Mcnamara, John" To: "Zhang, Qi Z" , "Wu, Jingjing" CC: "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [PATCH] doc: add knowing issue for i40e VF performance Thread-Index: AQHS8ySnuWYN3O8+j0WBKC1Fo1Q1g6JA5vSw Date: Sun, 2 Jul 2017 19:10:03 +0000 Message-ID: References: <20170702120644.3510-1-qi.z.zhang@intel.com> In-Reply-To: <20170702120644.3510-1-qi.z.zhang@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_PUBLIC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWM4ZDU0ZTctMjlhNS00MzJiLTlhNTMtMzMxZWQwMWM1MGRiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX1BVQkxJQyJ9XX1dfSwiU3ViamVjdExhYmVscyI6W10sIlRNQ1ZlcnNpb24iOiIxNi41LjkuMyIsIlRydXN0ZWRMYWJlbEhhc2giOiJTRHpCb1RGalo2QlRtYU5ZMERYeFhGK1FRaXdFdXVxRmZQSjJSamNxbWo4PSJ9 dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] doc: add knowing issue for i40e VF performance X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 Jul 2017 19:10:08 -0000 > -----Original Message----- > From: Zhang, Qi Z > Sent: Sunday, July 2, 2017 1:07 PM > To: Mcnamara, John ; Wu, Jingjing > > Cc: Zhang, Helin ; dev@dpdk.org; Zhang, Qi Z > > Subject: [PATCH] doc: add knowing issue for i40e VF performance >=20 > VF performance is limited by some kernel PCI setting. > Update the document to explain the knowing issue and work around solution= . >=20 > Signed-off-by: Qi Zhang > --- > doc/guides/nics/i40e.rst | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >=20 > diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index > 4d3c7ca..557d83d 100644 > --- a/doc/guides/nics/i40e.rst > +++ b/doc/guides/nics/i40e.rst > @@ -447,3 +447,27 @@ It means if APP has set the max bandwidth for that > TC, it comes to no effect. > It's suggested to set the strict priority mode for a TC that is latency > sensitive but no consuming much bandwidth. > + > +VF performance is impacted by PCI extended tag setting > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +To reach maximum NIC performance. PCI extended tag is required to be > enabled. > +DPDK I40E PF drvier will set this feature during initialization, but > +Kernel PF driver does not. So when running traffic on a VF which is > +managed by kernel PF driver, we saw significent NIC performance > +downgrade (for 64 bytes packet, there is about 25% linerate downgrade > +for 25G device and about 35% for 40G device). > + > +Solution: > + > +For kernel version >=3D 4.11, kernel's PCI driver will enale extended ta= g > +if it detects that device support extended tag. So by default, this is > not an issue. > +When extended tag is be disabled by occasionally, to re-enable it, see > below. > + > +For kernel version < 4.11, use setpci command to enable PCI extended > +flag > +1) get current value of PCI configure register setpci -s a8.w > +2) set bit 8 > +value =3D value | 0x100 > +3) set PCI configure register with new value. > +setpci -s a8.w=3D To use a numbered list in the doc you should do it like this: #. Get the current value of the PCI configure register:: setpci -s a8.w #. Set bit 8:: value =3D value | 0x100 #. Set the PCI configure register with new value:: setpci -s a8.w=3D John