From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id A65B45963 for ; Thu, 14 Aug 2014 09:35:59 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 14 Aug 2014 00:39:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,861,1400050800"; d="scan'208";a="558403670" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2014 00:39:02 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 14 Aug 2014 00:39:01 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.219]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.147]) with mapi id 14.03.0195.001; Thu, 14 Aug 2014 15:38:59 +0800 From: "Cao, Min" To: "Chen, Jing D" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/4] i40e: PF Add support for per-queue start/stop Thread-Index: AQHPt5K8k1Tp836lGkKqtusAZWd4AJvPtmDA Date: Thu, 14 Aug 2014 07:38:58 +0000 Message-ID: References: <1408001703-30919-1-git-send-email-jing.d.chen@intel.com> <1408001703-30919-3-git-send-email-jing.d.chen@intel.com> In-Reply-To: <1408001703-30919-3-git-send-email-jing.d.chen@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/4] i40e: PF Add support for per-queue start/stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Aug 2014 07:36:00 -0000 I will verified this next week. :) -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chen Jing D(Mark) Sent: Thursday, August 14, 2014 3:35 PM To: dev@dpdk.org Subject: [dpdk-dev] [PATCH 2/4] i40e: PF Add support for per-queue start/st= op From: "Chen Jing D(Mark)" I40E driver add function pointer to start/stop specific RX/TX queue. Signed-off-by: Chen Jing D(Mark) Reviewed-by: Konstantin Ananyev Reviewed-by: Changchun Ouyang Reviewed-by: Huawei Xie --- lib/librte_pmd_i40e/i40e_ethdev.c | 4 + lib/librte_pmd_i40e/i40e_rxtx.c | 112 +++++++++++++++++++++++++++++++++= ++++ lib/librte_pmd_i40e/i40e_rxtx.h | 4 + 3 files changed, 120 insertions(+), 0 deletions(-) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_e= thdev.c index 9ed31b5..81a1deb 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -232,6 +232,10 @@ static struct eth_dev_ops i40e_eth_dev_ops =3D { .vlan_offload_set =3D i40e_vlan_offload_set, .vlan_strip_queue_set =3D i40e_vlan_strip_queue_set, .vlan_pvid_set =3D i40e_vlan_pvid_set, + .rx_queue_start =3D i40e_dev_rx_queue_start, + .rx_queue_stop =3D i40e_dev_rx_queue_stop, + .tx_queue_start =3D i40e_dev_tx_queue_start, + .tx_queue_stop =3D i40e_dev_tx_queue_stop, .rx_queue_setup =3D i40e_dev_rx_queue_setup, .rx_queue_release =3D i40e_dev_rx_queue_release, .rx_queue_count =3D i40e_dev_rx_queue_count, diff --git a/lib/librte_pmd_i40e/i40e_rxtx.c b/lib/librte_pmd_i40e/i40e_rxt= x.c index 83b9462..323c004 100644 --- a/lib/librte_pmd_i40e/i40e_rxtx.c +++ b/lib/librte_pmd_i40e/i40e_rxtx.c @@ -1429,6 +1429,118 @@ i40e_xmit_pkts_simple(void *tx_queue, } =20 int +i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct i40e_vsi *vsi =3D I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private); + struct i40e_rx_queue *rxq; + int err =3D -1; + struct i40e_hw *hw =3D I40E_VSI_TO_HW(vsi); + uint16_t q_base =3D vsi->base_queue; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq =3D dev->data->rx_queues[rx_queue_id]; + + err =3D i40e_alloc_rx_queue_mbufs(rxq); + if (err) { + PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf\n"); + return err; + } + + rte_wmb(); + + /* Init the RX tail regieter. */ + I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1); + + err =3D i40e_switch_rx_queue(hw, rx_queue_id + q_base, TRUE); + + if (err) { + PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on\n", + rx_queue_id); + + i40e_rx_queue_release_mbufs(rxq); + i40e_reset_rx_queue(rxq); + } + } + + return err; +} + +int +i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct i40e_vsi *vsi =3D I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private); + struct i40e_rx_queue *rxq; + int err; + struct i40e_hw *hw =3D I40E_VSI_TO_HW(vsi); + uint16_t q_base =3D vsi->base_queue; + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq =3D dev->data->rx_queues[rx_queue_id]; + + err =3D i40e_switch_rx_queue(hw, rx_queue_id + q_base, FALSE); + + if (err) { + PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off\n", + rx_queue_id); + return err; + } + i40e_rx_queue_release_mbufs(rxq); + i40e_reset_rx_queue(rxq); + } + + return 0; +} + +int +i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct i40e_vsi *vsi =3D I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private); + int err =3D -1; + struct i40e_hw *hw =3D I40E_VSI_TO_HW(vsi); + uint16_t q_base =3D vsi->base_queue; + + PMD_INIT_FUNC_TRACE(); + + if (tx_queue_id < dev->data->nb_tx_queues) { + err =3D i40e_switch_tx_queue(hw, tx_queue_id + q_base, TRUE); + if (err) + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on\n", + tx_queue_id); + } + + return err; +} + +int +i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct i40e_vsi *vsi =3D I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private); + struct i40e_tx_queue *txq; + int err; + struct i40e_hw *hw =3D I40E_VSI_TO_HW(vsi); + uint16_t q_base =3D vsi->base_queue; + + if (tx_queue_id < dev->data->nb_tx_queues) { + txq =3D dev->data->tx_queues[tx_queue_id]; + + err =3D i40e_switch_tx_queue(hw, tx_queue_id + q_base, FALSE); + + if (err) { + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of\n", + tx_queue_id); + return err; + } + + i40e_tx_queue_release_mbufs(txq); + i40e_reset_tx_queue(txq); + } + + return 0; +} + +int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, diff --git a/lib/librte_pmd_i40e/i40e_rxtx.h b/lib/librte_pmd_i40e/i40e_rxt= x.h index 6db2faf..b67b4b3 100644 --- a/lib/librte_pmd_i40e/i40e_rxtx.h +++ b/lib/librte_pmd_i40e/i40e_rxtx.h @@ -152,6 +152,10 @@ struct i40e_tx_queue { bool q_set; /**< indicate if tx queue has been configured */ }; =20 +int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)= ; +int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)= ; +int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, uint16_t nb_desc, --=20 1.7.7.6