From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 5781C1F5 for ; Tue, 2 Dec 2014 03:56:45 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 01 Dec 2014 18:56:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="423823897" Received: from pgsmsx108.gar.corp.intel.com ([10.221.44.103]) by FMSMGA003.fm.intel.com with ESMTP; 01 Dec 2014 18:46:27 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by PGSMSX108.gar.corp.intel.com (10.221.44.103) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 2 Dec 2014 10:56:33 +0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.240]) by shsmsx102.ccr.corp.intel.com ([169.254.2.216]) with mapi id 14.03.0195.001; Tue, 2 Dec 2014 10:56:32 +0800 From: "Cao, Min" To: "Zang, Zhida" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] i40e: link flow control support Thread-Index: AQHQBKBo2fTUF0DaNEa0gedTT3FDfpx7rMkQ Date: Tue, 2 Dec 2014 02:56:32 +0000 Message-ID: References: <1416473922-8314-1-git-send-email-zhida.zang@intel.com> In-Reply-To: <1416473922-8314-1-git-send-email-zhida.zang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] i40e: link flow control support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Dec 2014 02:56:46 -0000 Tested-by: Min Cao Patch name: [dpdk-dev] [PATCH v2] i40e: link flow control support Test Flag: Tested-by Tester name: min.cao@intel.com Result summary: total 4 cases, 4 passed, 0 failed Test Case 1: =09 Name: flowctrl_off_pause_fwd_off Environment: OS: Fedora20 3.11.10-301.fc20.x86_64 gcc (GCC) 4.8.2 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz NIC: Fortville eagle/spirit=20 Test result: PASSED Test Case 2: =09 Name: flowctrl_on_pause_fwd_off Environment: OS: Fedora20 3.11.10-301.fc20.x86_64 gcc (GCC) 4.8.2 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz NIC: Fortville eagle/spirit=20 Test result: PASSED Test Case 3: =09 Name: flowctrl_off_pause_fwd_on Environment: OS: Fedora20 3.11.10-301.fc20.x86_64 gcc (GCC) 4.8.2 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz NIC: Fortville eagle/spirit=20 Test result: PASSED Test Case 4: =09 Name: flowctrl_on_pause_fwd_on Environment: OS: Fedora20 3.11.10-301.fc20.x86_64 gcc (GCC) 4.8.2 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz NIC: Fortville eagle/spirit=20 Test result: PASSED -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of zhida zang Sent: Thursday, November 20, 2014 4:59 PM To: dev@dpdk.org Subject: [dpdk-dev] [PATCH v2] i40e: link flow control support From: zzang Add link flow control support for i40e Signed-off-by: zhida zang --- lib/librte_pmd_i40e/i40e_ethdev.c | 155 ++++++++++++++++++++++++++++++++++= +++- lib/librte_pmd_i40e/i40e_ethdev.h | 10 +++ 2 files changed, 162 insertions(+), 3 deletions(-) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_e= thdev.c index a860af7..183b0be 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -69,6 +69,18 @@ #define I40E_DEFAULT_TX_WTHRESH 0 #define I40E_DEFAULT_TX_RSBIT_THRESH 32 =20 +/* Flow control default timer */ +#define I40E_DEFAULT_PAUSE_TIME 0xFFFFU + +/* Flow control default high water */ +#define I40E_DEFAULT_HIGH_WATER 0x1C40 + +/* Flow control default low water */ +#define I40E_DEFAULT_LOW_WATER 0x1A40 + +/* Flow control enable fwd bit */ +#define I40E_PRTMAC_FWD_CTRL 0x00000001 + /* Maximun number of MAC addresses */ #define I40E_NUM_MACADDR_MAX 64 #define I40E_CLEAR_PXE_WAIT_MS 200 @@ -98,6 +110,12 @@ =20 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */ =20 +/* Receive Packet Buffer size */ +#define I40E_RXPBSIZE (968 * 1024) + +/* Receive Average Packet Size in Byte*/ +#define I40E_PACKET_AVERAGE_SIZE 128 + static int eth_i40e_dev_init(\ __attribute__((unused)) struct eth_driver *eth_drv, struct rte_eth_dev *eth_dev); @@ -131,6 +149,8 @@ static void i40e_vlan_strip_queue_set(struct rte_eth_de= v *dev, static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int = on); static int i40e_dev_led_on(struct rte_eth_dev *dev); static int i40e_dev_led_off(struct rte_eth_dev *dev); +static int i40e_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); static int i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev, @@ -237,6 +257,7 @@ static struct eth_dev_ops i40e_eth_dev_ops =3D { .tx_queue_release =3D i40e_dev_tx_queue_release, .dev_led_on =3D i40e_dev_led_on, .dev_led_off =3D i40e_dev_led_off, + .flow_ctrl_get =3D i40e_flow_ctrl_get, .flow_ctrl_set =3D i40e_flow_ctrl_set, .priority_flow_ctrl_set =3D i40e_priority_flow_ctrl_set, .mac_addr_add =3D i40e_macaddr_add, @@ -358,6 +379,9 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_d= rv, pf->adapter =3D I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); pf->adapter->eth_dev =3D dev; pf->dev_data =3D dev->data; + pf->fc_conf.pause_time =3D I40E_DEFAULT_PAUSE_TIME; + pf->fc_conf.high_water[0] =3D I40E_DEFAULT_HIGH_WATER; + pf->fc_conf.low_water[0] =3D I40E_DEFAULT_LOW_WATER; =20 hw->back =3D I40E_PF_TO_ADAPTER(pf); hw->hw_addr =3D (uint8_t *)(pci_dev->mem_resource[0].addr); @@ -1516,12 +1540,137 @@ i40e_dev_led_off(struct rte_eth_dev *dev) } =20 static int -i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, - __rte_unused struct rte_eth_fc_conf *fc_conf) +i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_con= f) { + struct i40e_hw *hw =3D I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); + + fc_conf->pause_time =3D pf->fc_conf.pause_time; + fc_conf->high_water =3D (pf->fc_conf.high_water[0] * + I40E_PACKET_AVERAGE_SIZE) >> 10; + fc_conf->low_water =3D (pf->fc_conf.low_water[0] * + I40E_PACKET_AVERAGE_SIZE) >> 10; + + /* + * Return current mode according to actual setting + */ + switch (hw->fc.current_mode) { + case I40E_FC_FULL: + fc_conf->mode =3D RTE_FC_FULL; + break; + case I40E_FC_TX_PAUSE: + fc_conf->mode =3D I40E_FC_TX_PAUSE; + break; + case I40E_FC_RX_PAUSE: + fc_conf->mode =3D I40E_FC_RX_PAUSE; + break; + case I40E_FC_NONE: + fc_conf->mode =3D RTE_FC_NONE; + break; + default: + break; + }; + + return 0; +} + +static int +i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_con= f) +{ + uint32_t mflcn_reg, fctrl_reg, reg; + uint32_t max_high_water; + uint8_t i, aq_failure; + int err; + enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] =3D { + I40E_FC_NONE, + I40E_FC_RX_PAUSE, + I40E_FC_TX_PAUSE, + I40E_FC_FULL + }; + + max_high_water =3D I40E_RXPBSIZE >> 10; + if ((fc_conf->high_water > max_high_water) || + (fc_conf->high_water < fc_conf->low_water)) { + PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, " + "High_water must <=3D %d.", max_high_water); + return -EINVAL; + } + + struct i40e_hw *hw =3D I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); + hw->fc.requested_mode =3D rte_fcmode_2_i40e_fcmode[fc_conf->mode]; + + pf->fc_conf.pause_time =3D fc_conf->pause_time; + pf->fc_conf.high_water[0] =3D (fc_conf->high_water << 10) / + I40E_PACKET_AVERAGE_SIZE; + pf->fc_conf.low_water[0] =3D (fc_conf->low_water << 10) / + I40E_PACKET_AVERAGE_SIZE; + PMD_INIT_FUNC_TRACE(); =20 - return -ENOSYS; + err =3D i40e_set_fc(hw, &aq_failure, true); + if (err < 0) { + PMD_INIT_LOG(ERR, "failed to set link flow control," + "err =3D %d", aq_failure); + return err; + } + + if (i40e_is_40G_device(hw->device_id)) { + + /* + * Configure flow control refresh threshold, + * the value for stat_tx_pause_refresh_timer[8] + * is used for global pause operation. + */ + I40E_WRITE_REG(hw, + I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8), + pf->fc_conf.pause_time); + + /* configure the timer value included in transmitted pause + * frame, + * the value for stat_tx_pause_quanta[8] is used for global + * pause operation + */ + I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8), + pf->fc_conf.pause_time); + + fctrl_reg =3D I40E_READ_REG(hw, + I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL); + + if (fc_conf->mac_ctrl_frame_fwd !=3D 0) + fctrl_reg |=3D I40E_PRTMAC_FWD_CTRL; + else + fctrl_reg &=3D ~I40E_PRTMAC_FWD_CTRL; + + I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, + fctrl_reg); + } else { + /* Configure pause time (2 TCs per register) */ + reg =3D (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001; + for (i =3D 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++) + I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg); + + /* Configure flow control refresh threshold value */ + I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV, + pf->fc_conf.pause_time / 2); + + mflcn_reg =3D I40E_READ_REG(hw, I40E_PRTDCB_MFLCN); + + /* set or clear MFLCN.PMCF bit depending on configuration */ + if (fc_conf->mac_ctrl_frame_fwd !=3D 0) + mflcn_reg |=3D I40E_PRTDCB_MFLCN_PMCF_MASK; + else + mflcn_reg &=3D ~I40E_PRTDCB_MFLCN_PMCF_MASK; + + I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg); + } + + I40E_WRITE_REG(hw, I40E_GLRPB_PHW, pf->fc_conf.high_water[0]); + I40E_WRITE_REG(hw, I40E_GLRPB_PLW, pf->fc_conf.low_water[0]); + + I40E_WRITE_FLUSH(hw); + + return 0; } =20 static int diff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_e= thdev.h index e61d258..c793c2d 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.h +++ b/lib/librte_pmd_i40e/i40e_ethdev.h @@ -231,6 +231,14 @@ struct i40e_pf_vf { uint16_t lan_nb_qps; /* Actual queues allocated */ uint16_t reset_cnt; /* Total vf reset times */ }; +/* + * Structure to store private data for flow control. + */ +struct i40e_fc_conf { + uint16_t pause_time; /* Flow control pause timer */ + uint32_t high_water[I40E_MAX_TRAFFIC_CLASS]; /* FC high water */ + uint32_t low_water[I40E_MAX_TRAFFIC_CLASS]; /* FC low water */ +}; =20 /* * Structure to store private data specific for PF instance. @@ -264,6 +272,8 @@ struct i40e_pf { /* store VXLAN UDP ports */ uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; uint16_t vxlan_bitmap; /* Vxlan bit mask */ + + struct i40e_fc_conf fc_conf; /* Flow control conf */ }; =20 enum pending_msg { --=20 1.9.3