From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 1DB055960 for ; Sat, 10 Oct 2015 09:30:38 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 10 Oct 2015 00:30:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,662,1437462000"; d="scan'208";a="661545769" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 10 Oct 2015 00:30:37 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 10 Oct 2015 00:30:37 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 10 Oct 2015 00:30:37 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.96]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.194]) with mapi id 14.03.0248.002; Sat, 10 Oct 2015 15:30:35 +0800 From: "Wang, Xiao W" To: "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] e1000: enable igb TSO support Thread-Index: AQHQ+xu4NDVzF39jgkGKFN3j4opIwZ5joxoAgAC07KA= Date: Sat, 10 Oct 2015 07:30:34 +0000 Message-ID: References: <1443574955-30977-1-git-send-email-xiao.w.wang@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] e1000: enable igb TSO support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 Oct 2015 07:30:39 -0000 -----Original Message----- From: Zhang, Helin=20 Sent: Saturday, October 10, 2015 11:57 AM To: Wang, Xiao W; dev@dpdk.org Subject: RE: [dpdk-dev] [PATCH] e1000: enable igb TSO support > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wang Xiao W > Sent: Wednesday, September 30, 2015 9:03 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] e1000: enable igb TSO support >=20 > This patch enables igb TSO feature, the feature works on both PF and VF. > The TCP segmentation offload needs to write the offload related=20 > information into the advanced context descriptors, which is similar to ch= ecksum offload. >=20 > Signed-off-by: Wang Xiao W > --- > drivers/net/e1000/igb_ethdev.c | 6 +- > drivers/net/e1000/igb_rxtx.c | 198 > +++++++++++++++++++++++++---------------- > 2 files changed, 126 insertions(+), 78 deletions(-) >=20 > diff --git a/drivers/net/e1000/igb_ethdev.c=20 > b/drivers/net/e1000/igb_ethdev.c index c7e6d55..7728d37 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -1515,7 +1515,8 @@ eth_igb_infos_get(struct rte_eth_dev *dev,=20 > struct rte_eth_dev_info *dev_info) > DEV_TX_OFFLOAD_IPV4_CKSUM | > DEV_TX_OFFLOAD_UDP_CKSUM | > DEV_TX_OFFLOAD_TCP_CKSUM | > - DEV_TX_OFFLOAD_SCTP_CKSUM; > + DEV_TX_OFFLOAD_SCTP_CKSUM | > + DEV_TX_OFFLOAD_TCP_TSO; >=20 > switch (hw->mac.type) { > case e1000_82575: > @@ -1606,7 +1607,8 @@ eth_igbvf_infos_get(struct rte_eth_dev *dev,=20 > struct rte_eth_dev_info *dev_info) > DEV_TX_OFFLOAD_IPV4_CKSUM | > DEV_TX_OFFLOAD_UDP_CKSUM | > DEV_TX_OFFLOAD_TCP_CKSUM | > - DEV_TX_OFFLOAD_SCTP_CKSUM; > + DEV_TX_OFFLOAD_SCTP_CKSUM | > + DEV_TX_OFFLOAD_TCP_TSO; > switch (hw->mac.type) { > case e1000_vfadapt: > dev_info->max_rx_queues =3D 2; > diff --git a/drivers/net/e1000/igb_rxtx.c=20 > b/drivers/net/e1000/igb_rxtx.c index b13930e..be1710d 100644 > --- a/drivers/net/e1000/igb_rxtx.c > +++ b/drivers/net/e1000/igb_rxtx.c > @@ -76,7 +76,8 @@ > #define IGB_TX_OFFLOAD_MASK ( \ > PKT_TX_VLAN_PKT | \ > PKT_TX_IP_CKSUM | \ > - PKT_TX_L4_MASK) > + PKT_TX_L4_MASK | \ > + PKT_TX_TCP_SEG) >=20 > static inline struct rte_mbuf * > rte_rxmbuf_alloc(struct rte_mempool *mp) @@ -146,32 +147,40 @@ enum=20 > igb_advctx_num { }; >=20 > /** Offload features */ > -union igb_vlan_macip { > - uint32_t data; > +union igb_tx_offload { > + uint64_t data; > struct { > - uint16_t l2_l3_len; /**< 7bit L2 and 9b L3 lengths combined */ > - uint16_t vlan_tci; > - /**< VLAN Tag Control Identifier (CPU order). */ > - } f; > + uint64_t l3_len:9; /**< L3 (IP) Header Length. */ > + uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ > + uint64_t vlan_tci:16; /**< VLAN Tag Control Identifier(CPU order). */ > + uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ > + uint64_t tso_segsz:16; /**< TCP TSO segment size. */ > + > + /* uint64_t unused:8; */ > + }; > }; >=20 > /* > - * Compare mask for vlan_macip_len.data, > + * Compare mask for igb_tx_offload.data, > * should be in sync with igb_vlan_macip.f layout. As the union changed, above line comments should be reworded. Yes, I'll reword it, thanks. > * */ > -#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - > 16-bits. */ > -#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. > */ > -#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */ > -/** MAC+IP length. */ > -#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | > TX_IP_LEN_CMP_MASK) > +#define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFF /**< L2L3 header > mask. */ > +#define TX_VLAN_CMP_MASK 0x00000000FFFF0000 /**< Vlan mask. */ > +#define TX_TCP_LEN_CMP_MASK 0x000000FF00000000 /**< TCP > header mask. */ > +#define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000 /**< TSO > segsz mask. */ > +/** Mac + IP + TCP + Mss mask. */ > +#define TX_TSO_CMP_MASK \ > + (TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | > TX_TSO_MSS_CMP_MASK) >=20 > /** > * Strucutre to check if new context need be built > */ > struct igb_advctx_info { > uint64_t flags; /**< ol_flags related to context build. */ > - uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */ > - union igb_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */ > + /** tx offload: vlan, tso, l2-l3-l4 lengths. */ > + union igb_tx_offload tx_offload; > + /** compare mask for tx offload. */ > + union igb_tx_offload tx_offload_mask; > }; >=20 > /** > @@ -221,6 +230,8 @@ struct igb_tx_queue { > * Macro for VMDq feature for 1 GbE NIC. > */ > #define E1000_VMOLR_SIZE (8) > +#define IGB_TSO_MAX_HDRLEN (512) > +#define IGB_TSO_MAX_MSS (9216) >=20 >=20 > /************************************************************* > ******** > * > @@ -229,6 +240,23 @@ struct igb_tx_queue { >=20 > ************************************************************* > *********/ >=20 > /* > + *There're some limitaions in hardware for TCP segmentaion offload.=20 > + We Typo. Yes, I'll correct it. > +*should check whether the parameters are valid. > + */ > +static inline uint64_t > +check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para) { > + if (!(ol_req & PKT_TX_TCP_SEG)) > + return ol_req; > + if ((ol_para.tso_segsz > IGB_TSO_MAX_MSS) || (ol_para.l2_len + > + ol_para.l3_len + ol_para.l4_len > IGB_TSO_MAX_HDRLEN)) { > + ol_req &=3D ~PKT_TX_TCP_SEG; > + ol_req |=3D PKT_TX_TCP_CKSUM; > + } Add likely/unlikely, as it is in fast path. Ok. > + return ol_req; > +} > + > +/* > * Advanced context descriptor are almost same between igb/ixgbe > * This is a separate function, looking for optimization opportunity her= e > * Rework required to go with the pre-defined values. > @@ -237,64 +265,81 @@ struct igb_tx_queue { static inline void=20 > igbe_set_xmit_ctx(struct igb_tx_queue* txq, > volatile struct e1000_adv_tx_context_desc *ctx_txd, > - uint64_t ol_flags, uint32_t vlan_macip_lens) > + uint64_t ol_flags, union igb_tx_offload tx_offload) > { > uint32_t type_tucmd_mlhl; > uint32_t mss_l4len_idx; > uint32_t ctx_idx, ctx_curr; > - uint32_t cmp_mask; > + uint32_t vlan_macip_lens; > + union igb_tx_offload tx_offload_mask; >=20 > ctx_curr =3D txq->ctx_curr; > ctx_idx =3D ctx_curr + txq->ctx_start; >=20 > - cmp_mask =3D 0; > + tx_offload_mask.data =3D 0; > type_tucmd_mlhl =3D 0; >=20 > - if (ol_flags & PKT_TX_VLAN_PKT) { > - cmp_mask |=3D TX_VLAN_CMP_MASK; > - } > - > - if (ol_flags & PKT_TX_IP_CKSUM) { > - type_tucmd_mlhl =3D E1000_ADVTXD_TUCMD_IPV4; > - cmp_mask |=3D TX_MACIP_LEN_CMP_MASK; > - } > - > /* Specify which HW CTX to upload. */ > mss_l4len_idx =3D (ctx_idx << E1000_ADVTXD_IDX_SHIFT); > - switch (ol_flags & PKT_TX_L4_MASK) { > - case PKT_TX_UDP_CKSUM: > - type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_UDP | > + > + if (ol_flags & PKT_TX_VLAN_PKT) > + tx_offload_mask.data |=3D TX_VLAN_CMP_MASK; > + > + /* check if TCP segmentation required for this packet */ > + if (ol_flags & PKT_TX_TCP_SEG) { > + /* implies IP cksum in IPv4 */ > + if (ol_flags & PKT_TX_IP_CKSUM) > + type_tucmd_mlhl =3D E1000_ADVTXD_TUCMD_IPV4 | > + E1000_ADVTXD_TUCMD_L4T_TCP | > E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > - mss_l4len_idx |=3D sizeof(struct udp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > - cmp_mask |=3D TX_MACIP_LEN_CMP_MASK; > - break; > - case PKT_TX_TCP_CKSUM: > - type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_TCP | > + else > + type_tucmd_mlhl =3D E1000_ADVTXD_TUCMD_IPV6 | > + E1000_ADVTXD_TUCMD_L4T_TCP | > E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > - mss_l4len_idx |=3D sizeof(struct tcp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > - cmp_mask |=3D TX_MACIP_LEN_CMP_MASK; > - break; > - case PKT_TX_SCTP_CKSUM: > - type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_SCTP | > + > + tx_offload_mask.data |=3D TX_TSO_CMP_MASK; > + mss_l4len_idx |=3D tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT; > + mss_l4len_idx |=3D tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT; > + } else { /* no TSO, check if hardware checksum is needed */ > + if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK)) > + tx_offload_mask.data |=3D TX_MACIP_LEN_CMP_MASK; > + > + if (ol_flags & PKT_TX_IP_CKSUM) > + type_tucmd_mlhl =3D E1000_ADVTXD_TUCMD_IPV4; > + > + switch (ol_flags & PKT_TX_L4_MASK) { > + case PKT_TX_UDP_CKSUM: > + type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_UDP | > E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > - mss_l4len_idx |=3D sizeof(struct sctp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > - cmp_mask |=3D TX_MACIP_LEN_CMP_MASK; > - break; > - default: > - type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_RSV | > + mss_l4len_idx |=3D sizeof(struct udp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > + break; > + case PKT_TX_TCP_CKSUM: > + type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_TCP | > E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > - break; > + mss_l4len_idx |=3D sizeof(struct tcp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > + break; > + case PKT_TX_SCTP_CKSUM: > + type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_SCTP | > + E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > + mss_l4len_idx |=3D sizeof(struct sctp_hdr) << > E1000_ADVTXD_L4LEN_SHIFT; > + break; > + default: > + type_tucmd_mlhl |=3D E1000_ADVTXD_TUCMD_L4T_RSV | > + E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT; > + break; > + } I think configuring checksum of l2, l3, l4, and tso separately could be cle= arer. Please refer to the similar in i40e driver. Any reason of doing like this? I have read i40e driver, igb is more similar to ixgbe, the context descript= or layouts are almost the same. Tso configuring and checksum configuring lie in the if{} and else{} respect= ively, they share common=20 operations on context descriptor writing and offload recording. > } >=20 > - txq->ctx_cache[ctx_curr].flags =3D ol_flags; > - txq->ctx_cache[ctx_curr].cmp_mask =3D cmp_mask; > - txq->ctx_cache[ctx_curr].vlan_macip_lens.data =3D > - vlan_macip_lens & cmp_mask; > + txq->ctx_cache[ctx_curr].flags =3D ol_flags; > + txq->ctx_cache[ctx_idx].tx_offload.data =3D > + tx_offload_mask.data & tx_offload.data; > + txq->ctx_cache[ctx_idx].tx_offload_mask =3D tx_offload_mask; >=20 > ctx_txd->type_tucmd_mlhl =3D rte_cpu_to_le_32(type_tucmd_mlhl); > + vlan_macip_lens =3D (uint32_t)tx_offload.data; > ctx_txd->vlan_macip_lens =3D rte_cpu_to_le_32(vlan_macip_lens); > - ctx_txd->mss_l4len_idx =3D rte_cpu_to_le_32(mss_l4len_idx); > - ctx_txd->seqnum_seed =3D 0; > + ctx_txd->mss_l4len_idx =3D rte_cpu_to_le_32(mss_l4len_idx); > + ctx_txd->seqnum_seed =3D 0; > } >=20 > /* > @@ -303,20 +348,20 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq, > */ > static inline uint32_t > what_advctx_update(struct igb_tx_queue *txq, uint64_t flags, > - uint32_t vlan_macip_lens) > + union igb_tx_offload tx_offload) > { > /* If match with the current context */ > if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && > - (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data =3D=3D > - (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) { > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & > +tx_offload.data)))) { > return txq->ctx_curr; > } >=20 > /* If match with the second context */ > txq->ctx_curr ^=3D 1; > if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && > - (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data =3D=3D > - (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) { > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & > +tx_offload.data)))) { > return txq->ctx_curr; > } >=20 > @@ -333,14 +378,19 @@ tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags) >=20 > tmp =3D l4_olinfo[(ol_flags & PKT_TX_L4_MASK) !=3D=20 > PKT_TX_L4_NO_CKSUM]; > tmp |=3D l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) !=3D 0]; > + tmp |=3D l4_olinfo[(ol_flags & PKT_TX_TCP_SEG) !=3D 0]; Could you explain above line a bit? Why is it needed? Regards, Helin When tso is requested, checksum offload is concomitant. As you can see in t= est-pmd/csumonly.c, when TCP_SEG is added to ol_flags, TCP_CKSUM won't be added, then the above= line is needed. In ixgbe driver, similar logic exists. Best Regards, Wang Xiao > return tmp; > } >=20 > static inline uint32_t > tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags) { > + uint32_t cmdtype; > static uint32_t vlan_cmd[2] =3D {0, E1000_ADVTXD_DCMD_VLE}; > - return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) !=3D 0]; > + static uint32_t tso_cmd[2] =3D {0, E1000_ADVTXD_DCMD_TSE}; > + cmdtype =3D vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) !=3D 0]; > + cmdtype |=3D tso_cmd[(ol_flags & PKT_TX_TCP_SEG) !=3D 0]; > + return cmdtype; > } >=20 > uint16_t > @@ -354,14 +404,6 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf=20 > **tx_pkts, > volatile union e1000_adv_tx_desc *txd; > struct rte_mbuf *tx_pkt; > struct rte_mbuf *m_seg; > - union igb_vlan_macip vlan_macip_lens; > - union { > - uint16_t u16; > - struct { > - uint16_t l3_len:9; > - uint16_t l2_len:7; > - }; > - } l2_l3_len; > uint64_t buf_dma_addr; > uint32_t olinfo_status; > uint32_t cmd_type_len; > @@ -375,6 +417,7 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf=20 > **tx_pkts, > uint64_t tx_ol_req; > uint32_t new_ctx =3D 0; > uint32_t ctx =3D 0; > + union igb_tx_offload tx_offload =3D {0}; >=20 > txq =3D tx_queue; > sw_ring =3D txq->sw_ring; > @@ -399,16 +442,18 @@ eth_igb_xmit_pkts(void *tx_queue, struct=20 > rte_mbuf **tx_pkts, > tx_last =3D (uint16_t) (tx_id + tx_pkt->nb_segs - 1); >=20 > ol_flags =3D tx_pkt->ol_flags; > - l2_l3_len.l2_len =3D tx_pkt->l2_len; > - l2_l3_len.l3_len =3D tx_pkt->l3_len; > - vlan_macip_lens.f.vlan_tci =3D tx_pkt->vlan_tci; > - vlan_macip_lens.f.l2_l3_len =3D l2_l3_len.u16; > tx_ol_req =3D ol_flags & IGB_TX_OFFLOAD_MASK; >=20 > /* If a Context Descriptor need be built . */ > if (tx_ol_req) { > - ctx =3D what_advctx_update(txq, tx_ol_req, > - vlan_macip_lens.data); > + tx_offload.l2_len =3D tx_pkt->l2_len; > + tx_offload.l3_len =3D tx_pkt->l3_len; > + tx_offload.l4_len =3D tx_pkt->l4_len; > + tx_offload.vlan_tci =3D tx_pkt->vlan_tci; > + tx_offload.tso_segsz =3D tx_pkt->tso_segsz; > + tx_ol_req =3D check_tso_para(tx_ol_req, tx_offload); > + > + ctx =3D what_advctx_update(txq, tx_ol_req, tx_offload); > /* Only allocate context descriptor if required*/ > new_ctx =3D (ctx =3D=3D IGB_CTX_NUM); > ctx =3D txq->ctx_curr; > @@ -500,6 +545,8 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf=20 > **tx_pkts, > */ > cmd_type_len =3D txq->txd_type | > E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT; > + if (tx_ol_req & PKT_TX_TCP_SEG) > + pkt_len -=3D (tx_pkt->l2_len + tx_pkt->l3_len + tx_pkt->l4_len); > olinfo_status =3D (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT); #if > defined(RTE_LIBRTE_IEEE1588) > if (ol_flags & PKT_TX_IEEE1588_TMST) @@ -523,8 +570,7 @@=20 > eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, > txe->mbuf =3D NULL; > } >=20 > - igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, > - vlan_macip_lens.data); > + igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload); >=20 > txe->last_id =3D tx_last; > tx_id =3D txe->next_id; > @@ -532,8 +578,8 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf=20 > **tx_pkts, > } >=20 > /* Setup the TX Advanced Data Descriptor */ > - cmd_type_len |=3D tx_desc_vlan_flags_to_cmdtype(ol_flags); > - olinfo_status |=3D tx_desc_cksum_flags_to_olinfo(ol_flags); > + cmd_type_len |=3D tx_desc_vlan_flags_to_cmdtype(tx_ol_req); > + olinfo_status |=3D tx_desc_cksum_flags_to_olinfo(tx_ol_req); > olinfo_status |=3D (ctx << E1000_ADVTXD_IDX_SHIFT); > } >=20 > -- > 1.9.3