From: "Zhang, Tianfei" <tianfei.zhang@intel.com>
To: Shreyansh Jain <shreyansh.jain@nxp.com>,
"Xu, Rosen" <rosen.xu@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Doherty, Declan" <declan.doherty@intel.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"Yigit, Ferruh" <ferruh.yigit@intel.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Liu, Song" <song.liu@intel.com>, "Wu, Hao" <hao.wu@intel.com>,
"gaetan.rivet@6wind.com" <gaetan.rivet@6wind.com>,
"Wu, Yanglong" <yanglong.wu@intel.com>
Subject: Re: [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver
Date: Sun, 6 May 2018 00:28:37 +0000 [thread overview]
Message-ID: <BA6F50564D52C24884F9840E07E32DEC4DD75A7C@CDSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <HE1PR0402MB27800B8745D97FAC720467EC90850@HE1PR0402MB2780.eurprd04.prod.outlook.com>
> -----Original Message-----
> From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com]
> Sent: Sunday, May 6, 2018 2:43 AM
> To: Xu, Rosen <rosen.xu@intel.com>; dev@dpdk.org
> Cc: Doherty, Declan <declan.doherty@intel.com>; Richardson, Bruce
> <bruce.richardson@intel.com>; Yigit, Ferruh <ferruh.yigit@intel.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>; Zhang, Tianfei
> <tianfei.zhang@intel.com>; Liu, Song <song.liu@intel.com>; Wu, Hao
> <hao.wu@intel.com>; gaetan.rivet@6wind.com; Wu, Yanglong
> <yanglong.wu@intel.com>
> Subject: RE: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver
>
> Hello Rosen,
>
> > -----Original Message-----
> > From: Xu, Rosen [mailto:rosen.xu@intel.com]
> > Sent: Friday, May 4, 2018 7:41 PM
> > To: dev@dpdk.org
> > Cc: rosen.xu@intel.com; declan.doherty@intel.com;
> > bruce.richardson@intel.com; Shreyansh Jain <shreyansh.jain@nxp.com>;
> > ferruh.yigit@intel.com; konstantin.ananyev@intel.com;
> > tianfei.zhang@intel.com; song.liu@intel.com; hao.wu@intel.com;
> > gaetan.rivet@6wind.com; Yanglong Wu <yanglong.wu@intel.com>
> > Subject: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver
> >
> > From: Rosen Xu <rosen.xu@intel.com>
> >
> > Add Intel FPGA BUS Rawdev Driver which is based on librte_rawdev
> > library.
> >
> > Signed-off-by: Rosen Xu <rosen.xu@intel.com>
> > Signed-off-by: Yanglong Wu <yanglong.wu@intel.com>
> > Signed-off-by: Figo zhang <tianfei.zhang@intel.com>
> > ---
> > config/common_base | 1 +
> > drivers/raw/Makefile | 1 +
> > drivers/raw/ifpga_rawdev/Makefile | 36 ++
> > drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 599
> > +++++++++++++++++++++
> > drivers/raw/ifpga_rawdev/ifpga_rawdev.h | 37 ++
> > .../raw/ifpga_rawdev/rte_ifpga_rawdev_version.map | 4 +
> > mk/rte.app.mk | 1 +
> > 7 files changed, 679 insertions(+)
> > create mode 100644 drivers/raw/ifpga_rawdev/Makefile create mode
> > 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.c
> > create mode 100644 drivers/raw/ifpga_rawdev/ifpga_rawdev.h
> > create mode 100644
> > drivers/raw/ifpga_rawdev/rte_ifpga_rawdev_version.map
> >
>
> [...]
>
> > --- /dev/null
> > +++ b/drivers/raw/ifpga_rawdev/ifpga_rawdev.c
> > @@ -0,0 +1,599 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
> > +#include <string.h>
> > +#include <dirent.h>
> > +#include <sys/stat.h>
> > +#include <unistd.h>
> > +#include <sys/types.h>
> > +#include <fcntl.h>
> > +#include <rte_log.h>
> > +#include <rte_bus.h>
> > +#include <rte_eal_memconfig.h>
> > +#include <rte_malloc.h>
> > +#include <rte_devargs.h>
> > +#include <rte_memcpy.h>
> > +#include <rte_pci.h>
> > +#include <rte_bus_pci.h>
> > +#include <rte_kvargs.h>
> > +#include <rte_alarm.h>
> > +
> > +#include <rte_errno.h>
> > +#include <rte_per_lcore.h>
> > +#include <rte_memory.h>
> > +#include <rte_memzone.h>
> > +#include <rte_eal.h>
> > +#include <rte_common.h>
> > +#include <rte_bus_vdev.h>
> > +
> > +#include "base/opae_hw_api.h"
> > +#include "rte_rawdev.h"
> > +#include "rte_rawdev_pmd.h"
> > +#include "rte_bus_ifpga.h"
> > +#include "ifpga_common.h"
> > +#include "ifpga_logs.h"
> > +#include "ifpga_rawdev.h"
> > +
> > +int ifpga_rawdev_logtype;
> > +
> > +#define PCI_VENDOR_ID_INTEL 0x8086
> > +/* PCI Device ID */
> > +#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
> > +#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
> > +#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
> > +/* VF Device */
> > +#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
> > +#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
> > +#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
> > +#define RTE_MAX_RAW_DEVICE 10
> > +
> > +static const struct rte_pci_id pci_ifpga_map[] = {
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_PF_INT_5_X)
> > },
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_VF_INT_5_X)
> > },
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_PF_INT_6_X)
> > },
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_VF_INT_6_X)
> > },
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_PF_DSC_1_X)
> > },
> > + { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL,
> PCIE_DEVICE_ID_VF_DSC_1_X)
> > },
> > + { .vendor_id = 0, /* sentinel */ },
> > +};
> > +
> > +static int ifpga_fill_afu_dev(struct opae_accelerator *acc,
> > + struct rte_afu_device *afu_dev)
>
> Sorry, for nitpicking, but the function definitions should follow [1] model
> where return types are different lines than name.
>
> Something like:
>
> static int
> ifpga_fill_afu_dev(...)
>
>
> [1]
> http://dpdk.org/doc/guides/contributing/coding_style.html#c-function-defi
> nition-declaration-and-use
>
> This is valid for multiple function definitions. Can you please fix when you
> send v8 (which you might have to send for rebasing over master).
>
> > +{
> > + struct rte_mem_resource *res = afu_dev->mem_resource;
> > + struct opae_acc_region_info region_info;
> > + struct opae_acc_info info;
> > + unsigned long i;
> > + int ret;
> > +
> > + ret = opae_acc_get_info(acc, &info);
> > + if (ret)
> > + return ret;
> > +
> > + if (info.num_regions > PCI_MAX_RESOURCE)
> > + return -EFAULT;
> > +
> > + afu_dev->num_region = info.num_regions;
> > +
> > + for (i = 0; i < info.num_regions; i++) {
> > + region_info.index = i;
> > + ret = opae_acc_get_region_info(acc, ®ion_info);
> > + if (ret)
> > + return ret;
> > +
> > + if ((region_info.flags & ACC_REGION_MMIO) &&
> > + (region_info.flags & ACC_REGION_READ) &&
> > + (region_info.flags & ACC_REGION_WRITE)) {
> > + res[i].phys_addr = region_info.phys_addr;
> > + res[i].len = region_info.len;
> > + res[i].addr = region_info.addr;
> > + } else
> > + return -EFAULT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void ifpga_rawdev_info_get(struct rte_rawdev *dev,
> > + rte_rawdev_obj_t dev_info)
> > +{
> > + struct opae_adapter *adapter;
> > + struct opae_accelerator *acc;
> > + struct rte_afu_device *afu_dev;
> > +
> > + IFPGA_RAWDEV_PMD_FUNC_TRACE();
> > +
>
> [...]
>
> > +
> > +static int
> > +ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
> > + struct rte_pci_device *pci_dev)
> > +{
> > +
> > + IFPGA_RAWDEV_PMD_INFO("## %s\n", __func__);
>
> Actually, this is not INFO - this is debug. And, this seems like place for
> FUNC_TRACE call you have already defined in your log file.
>
> > + return ifpga_rawdev_create(pci_dev, rte_socket_id()); }
> > +
> > +static int ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev) {
> > + return ifpga_rawdev_destroy(pci_dev); }
> > +
> > +static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
> > + .id_table = pci_ifpga_map,
> > + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
> > + .probe = ifpga_rawdev_pci_probe,
> > + .remove = ifpga_rawdev_pci_remove,
> > +};
> > +
>
> [...]
>
> > diff --git a/drivers/raw/ifpga_rawdev/ifpga_rawdev.h
> > b/drivers/raw/ifpga_rawdev/ifpga_rawdev.h
> > new file mode 100644
> > index 0000000..9a09561
> > --- /dev/null
> > +++ b/drivers/raw/ifpga_rawdev/ifpga_rawdev.h
> > @@ -0,0 +1,37 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
> > +#ifndef _IFPGA_RAWDEV_H_
> > +#define _IFPGA_RAWDEV_H_
> > +
> > +extern int ifpga_rawdev_logtype;
> > +
> > +#define IFPGA_RAWDEV_PMD_LOG(level, fmt, args...) \
> > + rte_log(RTE_LOG_ ## level, ifpga_rawdev_logtype, "ifgpa: " fmt
> > "\n", \
> > + ##args)
>
> Another one.
> In many of your logs, you are adding '\n' in the end. Your PMD_LOG
> definition also has a '\n' - that is double new lines being printed for those
> logs.
>
> > +
> > +#define IFPGA_RAWDEV_PMD_FUNC_TRACE()
> IFPGA_RAWDEV_PMD_LOG(DEBUG,
> > ">>")
> > +
> > +#define IFPGA_RAWDEV_PMD_DEBUG(fmt, args...) \
> > + IFPGA_RAWDEV_PMD_LOG(DEBUG, fmt, ## args) #define
> > +IFPGA_RAWDEV_PMD_INFO(fmt, args...) \
> > + IFPGA_RAWDEV_PMD_LOG(INFO, fmt, ## args) #define
> > +IFPGA_RAWDEV_PMD_ERR(fmt, args...) \
> > + IFPGA_RAWDEV_PMD_LOG(ERR, fmt, ## args) #define
> > +IFPGA_RAWDEV_PMD_WARN(fmt, args...) \
> > + IFPGA_RAWDEV_PMD_LOG(WARNING, fmt, ## args)
> > +
> > +enum ifpga_rawdev_device_state {
> > + IFPGA_IDLE,
> > + IFPGA_READY,
> > + IFPGA_ERROR
> > +};
> > +
> > +static inline struct opae_adapter *
> > +ifpga_rawdev_get_priv(const struct rte_rawdev *rawdev) {
> > + return rawdev->dev_private;
> > +}
> > +
> > +#endif /* _IFPGA_RAWDEV_H_ */
>
> [...]
>
> There are some nitpicks highlighted in mail above - but nothing major. I
> would have no more comments (as well as review) for this.
> In principle, I am OK with this. For v8, please feel free to use for this patch:
>
> Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
>
> Thanks for the work and patience.
Thanks Shreyansh great support, we will send the v8 patches today.
next prev parent reply other threads:[~2018-05-06 0:28 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 13:45 [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-20 14:58 ` [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS Gaëtan Rivet
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 0/6] " Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-28 13:26 ` Gaëtan Rivet
2018-03-31 16:25 ` Xu, Rosen
2018-04-04 1:58 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro Rosen Xu
2018-03-28 13:27 ` Gaëtan Rivet
2018-03-31 16:26 ` Xu, Rosen
2018-04-04 2:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 3/6] mk/rte.app.mk: Add Intel FPGA Bus Build Configuration Macro To App Script Rosen Xu
2018-03-28 13:28 ` Gaëtan Rivet
2018-03-31 16:27 ` Xu, Rosen
2018-04-04 2:02 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 4/6] drivers/bus: Add Intel FPGA Bus Lib Code Rosen Xu
2018-03-28 13:52 ` Gaëtan Rivet
2018-03-31 16:31 ` Xu, Rosen
2018-04-02 4:25 ` Xu, Rosen
2018-04-02 4:31 ` Xu, Rosen
2018-04-04 4:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 5/6] drivers/raw/ifpga_rawdev: Add Intel FPGA Rawdev Driver Code Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 6/6] drivers/raw/ifpga_rawdev: Add Intel FPGA OPAE Share Code Rosen Xu
2018-03-28 9:37 ` [dpdk-dev] [PATCH v3 0/6] Introduce Intel FPGA BUS Bruce Richardson
2018-03-28 13:17 ` Gaëtan Rivet
2018-03-28 16:15 ` Zhang, Tianfei
2018-04-04 1:57 ` Xu, Rosen
2018-03-31 16:02 ` [dpdk-dev] [PATCH v4 0/3] " Rosen Xu
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 1/3] Add Intel FPGA BUS Lib Code Rosen Xu
2018-04-03 9:25 ` Shreyansh Jain
2018-04-04 1:44 ` Xu, Rosen
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-03 9:34 ` Shreyansh Jain
2018-04-04 1:49 ` Xu, Rosen
2018-04-04 11:31 ` Shreyansh Jain
2018-04-26 10:47 ` Xu, Rosen
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 1/3] Add Intel FPGA BUS Library Rosen Xu
2018-04-04 9:55 ` Bruce Richardson
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 11:59 ` Hemant Agrawal
2018-04-26 10:45 ` Xu, Rosen
2018-04-04 10:14 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Shreyansh Jain
2018-04-04 10:38 ` Richardson, Bruce
2018-04-04 11:11 ` Shreyansh Jain
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 0/5] " Xu, Rosen
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 1/5] iFPGA: Add Intel FPGA BUS Library Xu, Rosen
2018-05-02 13:14 ` Shreyansh Jain
2018-05-02 13:33 ` Zhang, Tianfei
2018-05-03 3:58 ` Tan, Jianfeng
2018-05-03 8:12 ` Tan, Jianfeng
2018-05-03 8:35 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-04 9:14 ` Shreyansh Jain
2018-05-04 9:04 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 4/5] iFPGA: add meson build Xu, Rosen
2018-05-02 9:46 ` Shreyansh Jain
2018-05-02 13:36 ` Zhang, Tianfei
2018-05-03 9:13 ` Shreyansh Jain
2018-05-03 15:12 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-05 18:42 ` Shreyansh Jain
2018-05-06 0:28 ` Zhang, Tianfei [this message]
2018-05-05 19:09 ` Shreyansh Jain
2018-05-06 0:52 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 4/5] iFPGA: add meson build Xu, Rosen
2018-05-05 18:21 ` Shreyansh Jain
2018-05-06 0:27 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-05 19:19 ` Shreyansh Jain
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 4/5] iFPGA: add meson build Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-06 11:54 ` Shreyansh Jain
2018-05-06 14:24 ` Zhang, Tianfei
2018-05-08 14:18 ` [dpdk-dev] [PATCH v9 0/4] Introduce Intel FPGA BUS Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-08 14:42 ` Thomas Monjalon
2018-05-09 1:25 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 2/4] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-08 14:45 ` Thomas Monjalon
2018-05-09 1:24 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 3/4] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 4/4] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-08 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 8:43 ` Wu, Jingjing
2018-05-10 12:20 ` Xu, Rosen
2018-05-10 22:39 ` Wu, Jingjing
2018-05-11 3:18 ` Xu, Rosen
2018-05-10 12:26 ` Zhang, Qi Z
2018-05-10 13:29 ` Xu, Rosen
2018-05-10 13:48 ` Zhang, Qi Z
2018-05-10 13:58 ` Xu, Rosen
2018-05-10 14:11 ` Zhang, Qi Z
2018-05-10 13:51 ` Xu, Rosen
2018-05-10 13:58 ` Zhang, Qi Z
2018-05-10 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-09 14:47 ` Thomas Monjalon
2018-05-09 15:33 ` Zhang, Tianfei
2018-05-09 15:37 ` Bruce Richardson
2018-05-09 15:57 ` Zhang, Tianfei
2018-05-10 13:31 ` Xu, Rosen
2018-05-10 9:21 ` Wu, Jingjing
2018-05-10 13:16 ` Xu, Rosen
2018-05-11 3:21 ` Xu, Rosen
2018-05-10 14:24 ` Zhang, Qi Z
2018-05-11 3:16 ` Xu, Rosen
2018-05-11 5:36 ` Zhang, Qi Z
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 12:11 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Zhang, Qi Z
2018-05-11 13:45 ` Xu, Rosen
2018-05-11 15:12 ` Thomas Monjalon
2018-05-14 9:58 ` [dpdk-dev] [PATCH] raw/ifpga/base: fix compile error on ia32 icc compiler Xu, Rosen
2018-05-14 10:20 ` De Lara Guarch, Pablo
2018-05-14 10:32 ` Thomas Monjalon
2018-05-16 13:48 ` [dpdk-dev] [PATCH] drivers/bus/ifpga/: fix Coverity issue Rosen Xu
2018-05-21 14:00 ` [dpdk-dev] [dpdk-stable] " Thomas Monjalon
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 1/3] bus/ifpga: fix error control flow issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 2/3] bus/ifpga: fix resource leaks issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 3/3] bus/ifpga: fix null pointer dereferences issue Rosen Xu
2018-05-22 15:15 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Thomas Monjalon
2018-05-23 0:26 ` Xu, Rosen
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