From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id B892AA0557;
	Fri, 10 Jun 2022 08:09:50 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id 67FA240689;
	Fri, 10 Jun 2022 08:09:50 +0200 (CEST)
Received: from mga05.intel.com (mga05.intel.com [192.55.52.43])
 by mails.dpdk.org (Postfix) with ESMTP id DD7BF40221;
 Fri, 10 Jun 2022 08:09:47 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
 d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
 t=1654841388; x=1686377388;
 h=from:to:cc:subject:date:message-id:references:
 in-reply-to:content-transfer-encoding:mime-version;
 bh=KOAdVnH+bkGZUbGiNMKrOkp9Z5a73mO9VAeBHcxx+7U=;
 b=GwyisJBI54YMZSOsAEmkh4mqXyI/JJCNAm9W374TCiYleKTr46PNyAVH
 PA1jlz6jyNvtt/PiGVe4KgS2+CogWWCWY+M5BoExPjPXTfyH0vC/RIQgR
 p/06K6b6lE2y73yycUHZ5sDSikKRFcmqIN+rxjVV6MOl5OaHO52P0gdOr
 ilPawbsYJhx5d3mifQYAx0q49AMpIAclLo3klmxu0Ha1Cbq20dht4zQsB
 9N2Ab8+qPKAZELvoPY00vJmZRCE4XFo1UNpzkL8msHomEQoaoIfEL4ECu
 IXChfC0sAhSdcp+T7JDO+DgVVE7zVarkZe+2V/7Kc8cKmvsmZoPv0GwOT w==;
X-IronPort-AV: E=McAfee;i="6400,9594,10373"; a="363857675"
X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="363857675"
Received: from orsmga001.jf.intel.com ([10.7.209.18])
 by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
 09 Jun 2022 23:09:46 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="616317798"
Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86])
 by orsmga001.jf.intel.com with ESMTP; 09 Jun 2022 23:09:46 -0700
Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by
 fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.2308.27; Thu, 9 Jun 2022 23:09:45 -0700
Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by
 fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.2308.27 via Frontend Transport; Thu, 9 Jun 2022 23:09:45 -0700
Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.176)
 by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
 15.1.2308.27; Thu, 9 Jun 2022 23:09:45 -0700
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
 b=cOUJRN/5acoU0EDBj/2ypmUGZw7dUU1RkvrRJ+g1Foz9VPLsiNjCGqI9B6Oc4Ci/R4QueJ/W0TaASOWjHr1fdF28zvz02YK3uIR+UqfHi1oPyQyO/9iEue84cgeMgs28V+5CJnupeXxXNGxYI2c+Eac+3qEZh7PPe57MVb4RcVy3bRinuAUlk1LQ15WUYqSOCNSUeoQJHyg+LGJIsyVR+jy+8DCI7RvhmBZ0JbeP03fmDQm1CBbl+W17K2xbsaczvolJ3bYD8580z2xx0/08O0iFSm1ODMqTMe93qFKwuALdq9aayjzGKjcdDIisW7WehmqIkEwcvlU9zXiEAfE3uw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; 
 s=arcselector9901;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;
 bh=mCcJUGwTPQp5Nm1K+imCOYNMRV1cKH7DYbm6Dl6MpBQ=;
 b=ieuBjzbwjaxp4ctp8RvpWiq8Bfcu81PIABKOxRcR7ar64T8daYa9ahueeceB1gkh6vlPE/InsJwEkkp6l0n0c1a05UEPK4Orf3Xt4sBwZ1NSdEce/ER23Mu9DxWNQ6iEcQNqoKbfyvOvTE8YedPTluFMYdLjEsmEtaZ/HUVhHzE2HcdgbUMDm+Zpry2AxeR9xS0OnnW38PU4ajvUW4AGcSnz97bivsvvhmJ8dCQcZOhnumq+XScmAXx1eAYwugtIQFIqtWCPcjfMds9aWvWOsjhDxMD7UXVYN+Edo+H/X7+H/C9ULRzJjRimry5kUDveylPiinxytZjpj1K/tZa/Ew==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass
 smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;
 dkim=pass header.d=intel.com; arc=none
Received: from BL1PR11MB5477.namprd11.prod.outlook.com (2603:10b6:208:31f::19)
 by MN0PR11MB5963.namprd11.prod.outlook.com (2603:10b6:208:372::10)
 with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Fri, 10 Jun
 2022 06:09:44 +0000
Received: from BL1PR11MB5477.namprd11.prod.outlook.com
 ([fe80::d866:27cd:1ae5:db2c]) by BL1PR11MB5477.namprd11.prod.outlook.com
 ([fe80::d866:27cd:1ae5:db2c%5]) with mapi id 15.20.5332.013; Fri, 10 Jun 2022
 06:09:44 +0000
From: "Zhang, Tianfei" <tianfei.zhang@intel.com>
To: "Huang, Wei" <wei.huang@intel.com>, "dev@dpdk.org" <dev@dpdk.org>,
 "thomas@monjalon.net" <thomas@monjalon.net>, "nipun.gupta@nxp.com"
 <nipun.gupta@nxp.com>, "hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>
CC: "stable@dpdk.org" <stable@dpdk.org>, "Xu, Rosen" <rosen.xu@intel.com>,
 "Zhang, Qi Z" <qi.z.zhang@intel.com>
Subject: RE: [PATCH v7 1/5] raw/ifpga: introduce AFU driver framework
Thread-Topic: [PATCH v7 1/5] raw/ifpga: introduce AFU driver framework
Thread-Index: AQHYe9K78iV/9sFKH0WxljQrg7yCga1IKX+g
Date: Fri, 10 Jun 2022 06:09:44 +0000
Message-ID: <BL1PR11MB54771B5ADE6C8CCF54897CBAE3A69@BL1PR11MB5477.namprd11.prod.outlook.com>
References: <1654742650-7214-1-git-send-email-wei.huang@intel.com>
 <1654760242-7832-1-git-send-email-wei.huang@intel.com>
 <1654760242-7832-2-git-send-email-wei.huang@intel.com>
In-Reply-To: <1654760242-7832-2-git-send-email-wei.huang@intel.com>
Accept-Language: zh-CN, en-US
Content-Language: en-US
X-MS-Has-Attach: 
X-MS-TNEF-Correlator: 
dlp-product: dlpe-windows
dlp-version: 11.6.500.17
dlp-reaction: no-action
authentication-results: dkim=none (message not signed)
 header.d=none;dmarc=none action=none header.from=intel.com;
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: febfe140-8de9-434f-75df-08da4aa7d04b
x-ms-traffictypediagnostic: MN0PR11MB5963:EE_
x-microsoft-antispam-prvs: <MN0PR11MB5963DA1D99320F7860E5255CE3A69@MN0PR11MB5963.namprd11.prod.outlook.com>
x-ms-exchange-senderadcheck: 1
x-ms-exchange-antispam-relay: 0
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: 3yCq3QHWGnPiphKO2DMncPp3RNMHFYrylZv0tIHpBldA96TWZFaE3xATllpbDviM2uyCfmS1WfxUukVM929vnK4Atbc7dcnxTM5nmSo9Cm8yd4TEPpdBOFHswVxUw/wiR/jRKoGMU54aa+5kMM7cfqMrG5NfV2Gq7SLXuj6HQZHCjQWYQtGtK6++HQm2keyl/VaUD5+/zQ5ejqjF5BYhh4p4fjkcExGgBtl2rMoR0UIOhU76iJds9KYFOJ88itM3f3hL18JoTyPcIhcHP8AdIEbx0KsrINP0O2jRKJ11lT5mCw7pxXDJPZLa+mT3E/lFD4s4+Xl0ubJIP9f5LwBsx+I9cxYEodwUORyBkoLQ32PtCucMA+vKsDcvgzNUL+C/KOoXw7poTWvGcuUFUjywxALM+QK5rBMmadv5dGPq+H9W2aNwZyVCsrXa/khPcww90MLN1Ima05EfXYgyTk2Kewfu1TH1US09+ga/C7NzOv6xblNwmBJNFcRSH3OEewILeHefMJxCQXiEwgfpGtIAhRyEkEOToQ5oIa44dm4MS+DBCLGze/c6k3vzMVsP2NzATEJFexNKbxYHe7p/QhBL42gFx8LQRDH08iUKwUHML9nhJHkuO2bEhR0F/DAYLEWFoXQ+VqewtBg61F2cGphQXl9IX85sux7cR5eKwM+6gBnRq3L2saWfSWqQiN1EJ+YD5mRmGwMty4tCDFmuFFac+g==
x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;
 IPV:NLI; SFV:NSPM; H:BL1PR11MB5477.namprd11.prod.outlook.com; PTR:; CAT:NONE;
 SFS:(13230001)(366004)(52536014)(8936002)(2906002)(122000001)(64756008)(76116006)(186003)(8676002)(110136005)(66556008)(66476007)(66446008)(83380400001)(55016003)(66946007)(508600001)(107886003)(4326008)(316002)(82960400001)(38100700002)(38070700005)(54906003)(5660300002)(33656002)(30864003)(9686003)(7696005)(6506007)(53546011)(71200400001)(86362001);
 DIR:OUT; SFP:1102; 
x-ms-exchange-antispam-messagedata-chunkcount: 2
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?zFIcdHNmVTlebXDiokJ+vhNpXmN4UQ2xkXGA6/+WaFt1OK5QWSLB9XYNPgC0?=
 =?us-ascii?Q?EebAHrqrrBPg8d+d0HdN1wOFNFVAYtTfPWXDYnS4sFMMyQp9QEaP+mfJEVP5?=
 =?us-ascii?Q?RPlJlG/a4dEVKNosR1RTl0VeLqkh7ST4nNz5LprYN0J/xohjZ9UpSDK/koj0?=
 =?us-ascii?Q?2FMycwOk1RH+XyJ05OGejmTpWdQvLSfDS2ZEdNKThjoNHTX+7nFxzHOF3Rdh?=
 =?us-ascii?Q?9NWV0TosexnOApNZmBv9Qj+c+LWXXdnJamLRCFuhSeM+ZOPBS3pHKSldd5Pb?=
 =?us-ascii?Q?n8sovWkm4vpr+ojP3p7CK64PUKK3HYpvz1I2xOeUF08GDhJLGThtXef77tfu?=
 =?us-ascii?Q?0+QnEz2I0xy6oT7mldsCYRQrxFDSiiZ/EwfYawFpSKChZOAOg2pwYzTMrNwM?=
 =?us-ascii?Q?/8UVuRUr4GTjDu4b4Dig7OuM7vaIPoLERTCX8qQb/+IrfXQizL2qxzwpesjt?=
 =?us-ascii?Q?93jsPxbTPbGrC5AtpJdj7kzcXATGSDHnI14NDkYnQ6rOnryi/RKBdBZvUwE3?=
 =?us-ascii?Q?RV/DV916oLD/Pqsk4FHTqKFqZRR5mJCzYnl6VQWZ46wCCgtWCYx4UWOIHzLo?=
 =?us-ascii?Q?dyEWPwOVLT2OPVf396fpjAHfB2R4q5ZwlrO1XLzuUwZQfsVk9i4aTXaMCJ0T?=
 =?us-ascii?Q?yaUXxw1duirk67CR2fAPLNVSTpus4B6Qwddzj7qjd2kzqbBYZ9OXdX4lYcjP?=
 =?us-ascii?Q?sdtAfUrXHfYBFkoe86fHawv+RYKFnrboG2jmd+yP4NSGRlljG6YvynedI+0h?=
 =?us-ascii?Q?Sn3jLoqvjFG5aFc+v1p/4uPK6pQm4w6HLVOgcRv/AmVXOVrML+f8frUFBuBC?=
 =?us-ascii?Q?e8jah36WL+hLayD3huXhe1N5rZJD6zhMMWwa2hl1anUXhWA06JFLlQ853ys4?=
 =?us-ascii?Q?O4Hhrvj08sIyw/FI1FY4DbQXy7IyaB8edGLmCEP9/uTfVwnUFDLOEYLXCtCm?=
 =?us-ascii?Q?7j5Bj8MYNWGZ0LB12EMwN4VR76vPT7I6ZLglivj6Z9EHGgWv7UMdgjJ36WDK?=
 =?us-ascii?Q?oYk+075T4VUorFf83cRa2HTdRoW1US8JZr7dySHrIRIUCvpGBlTVw4EITWTR?=
 =?us-ascii?Q?5goEuSALARBaZyPTHZAfkDutqmlwz1npYBfAAuF6d8y13jWS3hPTDd5hzPPh?=
 =?us-ascii?Q?P++Tq4ftYPNZIB0BiJOMwvEXn+QucloUocUXNnJ8V/W5luhIGWaIMWnrTqs+?=
 =?us-ascii?Q?OstyrN3arJ6oWa5hGVkBMW5FnHTm1Zucws4crI241T8XKYwdaPmQ6AEo7km/?=
 =?us-ascii?Q?NaZFn5QMm2yZP/PFy5Oqle1D72Tq7fAjxVSYGZL70VE26tUwXPA0bS0JRL8z?=
 =?us-ascii?Q?L8yip4RH2GIYq+I4yu856z4hSrdTSz+CQM4PM7gZ1v9SMu39sny/ySPC9Zym?=
 =?us-ascii?Q?csSbtyCX+tl0URsFz1YgGsSUlGAI6p1BDZ52Hq7L3yjEFbuWN1vV8BUXcuuQ?=
 =?us-ascii?Q?ZKFWV5vn/Kz2nVwiWwDmoZlowdYdH4IUe5HUY+xAGbtMBOS34UG76Zjss7Q2?=
 =?us-ascii?Q?uAhEzj6GAdGexo/PFqvIB8ZE5VejTG9EM4Pke1DkOSRZ95OR/uUIk7OBBYd2?=
 =?us-ascii?Q?i6C9us7cSoF5JoKCqRnwbQk2tRmEbG+RbK39UZIwEt+LVxs3AIdPkNaBb7ks?=
 =?us-ascii?Q?RYP2a7k1LOFJbUpbF2ah+oziHw+dwqzxDcwcI58H2eVhMnMcL0Ed6cbJOMH8?=
 =?us-ascii?Q?1gp0af3YQ8ThlVUfRWcPF4rP5U15AYmHCfzyq+MjqvM792k+z9NV2R3UChKB?=
 =?us-ascii?Q?sDuQi+vPRRA2rrRArIPHx9yPz1LoIjcfxIYUKkT9MMktnO+HGGNP8ZE9f8cY?=
x-ms-exchange-antispam-messagedata-1: IUYSea93L55fO4QB6PRN7xyoL+HfF99d/V0=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: BL1PR11MB5477.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: febfe140-8de9-434f-75df-08da4aa7d04b
X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jun 2022 06:09:44.0321 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: nCeCWWm69amsPY0cy+reOj5Zz9uScLOLdZ+enO/TzkMSk6Dn1ZGZ39Uf2GAbo7s6zQg6DL5xAOACmYI50Ecrrw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR11MB5963
X-OriginatorOrg: intel.com
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org



> -----Original Message-----
> From: Huang, Wei <wei.huang@intel.com>
> Sent: Thursday, June 9, 2022 3:37 PM
> To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com;
> hemant.agrawal@nxp.com
> Cc: stable@dpdk.org; Xu, Rosen <rosen.xu@intel.com>; Zhang, Tianfei
> <tianfei.zhang@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Huang, Wei
> <wei.huang@intel.com>
> Subject: [PATCH v7 1/5] raw/ifpga: introduce AFU driver framework
>=20
> AFU (Acceleration Function Unit) is part of FPGA and enumerated by ifpga =
driver.
> This driver implements common AFU device interfaces and exposes them to
> application as standard raw device APIs.
> Normally application can operate specified AFU as below, 1. call
> rte_rawdev_pmd_get_named_dev() to find AFU device.
> 2. call rte_rawdev_configure() to initialize AFU device.
> 3. call rte_rawdev_selftest() to test AFU device.
>=20
> Signed-off-by: Wei Huang <wei.huang@intel.com>
> ---
> v2: fix typo
> ---
> v3: fix build error in FreeBSD13-64, UB2004-32 and UB2204-32
> ---
> v4: fix coding style issue and build error in FreeBSD13-64
> ---
> v5: split patch into several patches
> ---
> v6: move source files to ifpga and rename, use spinlock
> ---
>  drivers/raw/ifpga/afu_pmd_core.c | 453
> +++++++++++++++++++++++++++++++++++++++
>  drivers/raw/ifpga/afu_pmd_core.h |  76 +++++++
>  drivers/raw/ifpga/meson.build    |   2 +-
>  3 files changed, 530 insertions(+), 1 deletion(-)  create mode 100644
> drivers/raw/ifpga/afu_pmd_core.c  create mode 100644
> drivers/raw/ifpga/afu_pmd_core.h
>=20
> diff --git a/drivers/raw/ifpga/afu_pmd_core.c
> b/drivers/raw/ifpga/afu_pmd_core.c
> new file mode 100644
> index 0000000..a24b517
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_core.c
> @@ -0,0 +1,453 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright 2022 Intel Corporation
> + *
> + * AFU is Acceleration Function Unit in FPGA, it is enumerated by ifpga =
pmd.
> + * Suppose AFU is found in FPGA at PCI address 31:00.0, then you can
> +create
> + * and test a AFU device by following steps in application.
> + * 1. rte_vdev_init("ifpga_rawdev_cfg0", "ifpga=3D31:00.0,port=3D0")
> + * 2. rawdev =3D rte_rawdev_pmd_get_named_dev("afu_0|31:00.0")
> + * 3. rte_rawdev_configure(rawdev->dev_id, &cfg, sizeof(cfg))
> + * 4. rte_rawdev_selftest(rawdev->dev_id)
> + * 5. rte_vdev_uninit("ifpga_rawdev_cfg0")
> + *
> + * AFU device name format used in rte_rawdev_pmd_get_named_dev is
> + * "afu_[port]|[BDF]". Please refer to OPAE documentation for the
> +meaning of
> + * port. Each AFU device has specific configuration data, they are
> +defined
> + * in rte_pmd_afu.h.
> + *
> + */
> +
> +#include <errno.h>
> +#include <stdio.h>
> +#include <stdint.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <unistd.h>
> +#include <fcntl.h>
> +#include <poll.h>
> +#include <sys/eventfd.h>
> +
> +#include <rte_eal.h>
> +#include <rte_malloc.h>
> +#include <rte_memzone.h>
> +#include <rte_rawdev_pmd.h>
> +
> +#include "afu_pmd_core.h"
> +
> +static struct rte_afu_uuid afu_pmd_uuid_map[AFU_RAWDEV_MAX_DRVS+1];
> +TAILQ_HEAD(afu_drv_list, afu_rawdev_drv); static struct afu_drv_list
> +afu_pmd_list =3D TAILQ_HEAD_INITIALIZER(afu_pmd_list);
> +
> +static inline int afu_rawdev_trylock(struct afu_rawdev *dev) {
> +	if (!dev || !dev->sd)
> +		return 0;
> +
> +	return rte_spinlock_trylock(&dev->sd->lock);
> +}
> +
> +static inline void afu_rawdev_unlock(struct afu_rawdev *dev) {
> +	if (!dev || !dev->sd)
> +		return;
> +
> +	rte_spinlock_unlock(&dev->sd->lock);
> +}
> +
> +static int afu_rawdev_configure(const struct rte_rawdev *rawdev,
> +	rte_rawdev_obj_t config, size_t config_size) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return -ENODEV;
> +
> +	if (dev->ops && dev->ops->config)
> +		ret =3D (*dev->ops->config)(dev, config, config_size);
> +
> +	return ret;
> +}
> +
> +static int afu_rawdev_start(struct rte_rawdev *rawdev) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return -ENODEV;
> +
> +	ret =3D afu_rawdev_trylock(dev);
> +	if (!ret) {
> +		IFPGA_RAWDEV_PMD_WARN("AFU is busy, please start it
> later");
> +		return ret;
> +	}
> +
> +	if (dev->ops && dev->ops->start)
> +		ret =3D (*dev->ops->start)(dev);
> +
> +	afu_rawdev_unlock(dev);
> +
> +	return ret;
> +}
> +
> +static void afu_rawdev_stop(struct rte_rawdev *rawdev) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return;
> +
> +	ret =3D afu_rawdev_trylock(dev);
> +	if (!ret) {
> +		IFPGA_RAWDEV_PMD_WARN("AFU is busy, please stop it
> later");
> +		return;
> +	}
> +
> +	if (dev->ops && dev->ops->stop)
> +		ret =3D (*dev->ops->stop)(dev);
> +
> +	afu_rawdev_unlock(dev);
> +}
> +
> +static int afu_rawdev_close(struct rte_rawdev *rawdev) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return -ENODEV;
> +
> +	if (dev->ops && dev->ops->close)
> +		ret =3D (*dev->ops->close)(dev);
> +
> +	return ret;
> +}
> +
> +static int afu_rawdev_reset(struct rte_rawdev *rawdev) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return -ENODEV;
> +
> +	ret =3D afu_rawdev_trylock(dev);
> +	if (!ret) {
> +		IFPGA_RAWDEV_PMD_WARN("AFU is busy, please reset it
> later");
> +		return ret;
> +	}
> +
> +	if (dev->ops && dev->ops->reset)
> +		ret =3D (*dev->ops->reset)(dev);
> +
> +	afu_rawdev_unlock(dev);
> +
> +	return ret;
> +}
> +
> +static int afu_rawdev_selftest(uint16_t dev_id) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	if (!rte_rawdev_pmd_is_valid_dev(dev_id))
> +		return -ENODEV;
> +
> +	dev =3D afu_rawdev_get_priv(&rte_rawdevs[dev_id]);
> +	if (!dev)
> +		return -ENOENT;
> +
> +	ret =3D afu_rawdev_trylock(dev);
> +	if (!ret) {
> +		IFPGA_RAWDEV_PMD_WARN("AFU is busy, please test it
> later");
> +		return ret;
> +	}
> +
> +	if (dev->ops && dev->ops->test)
> +		ret =3D (*dev->ops->test)(dev);
> +
> +	afu_rawdev_unlock(dev);
> +
> +	return ret;
> +}
> +
> +static int afu_rawdev_dump(struct rte_rawdev *rawdev, FILE *f) {
> +	struct afu_rawdev *dev =3D NULL;
> +	int ret =3D 0;
> +
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		return -ENODEV;
> +
> +	if (dev->ops && dev->ops->dump)
> +		ret =3D (*dev->ops->dump)(dev, f);
> +
> +	return ret;
> +}
> +
> +static const struct rte_rawdev_ops afu_rawdev_ops =3D {
> +	.dev_info_get =3D NULL,
> +	.dev_configure =3D afu_rawdev_configure,
> +	.dev_start =3D afu_rawdev_start,
> +	.dev_stop =3D afu_rawdev_stop,
> +	.dev_close =3D afu_rawdev_close,
> +	.dev_reset =3D afu_rawdev_reset,
> +
> +	.queue_def_conf =3D NULL,
> +	.queue_setup =3D NULL,
> +	.queue_release =3D NULL,
> +	.queue_count =3D NULL,
> +
> +	.attr_get =3D NULL,
> +	.attr_set =3D NULL,
> +
> +	.enqueue_bufs =3D NULL,
> +	.dequeue_bufs =3D NULL,
> +
> +	.dump =3D afu_rawdev_dump,
> +
> +	.xstats_get =3D NULL,
> +	.xstats_get_names =3D NULL,
> +	.xstats_get_by_name =3D NULL,
> +	.xstats_reset =3D NULL,
> +
> +	.firmware_status_get =3D NULL,
> +	.firmware_version_get =3D NULL,
> +	.firmware_load =3D NULL,
> +	.firmware_unload =3D NULL,
> +
> +	.dev_selftest =3D afu_rawdev_selftest,
> +};
> +
> +static int afu_shared_data_alloc(const char *name,
> +	struct afu_shared_data **data, int socket_id) {
> +	const struct rte_memzone *mz;
> +	char mz_name[RTE_MEMZONE_NAMESIZE];
> +	struct afu_shared_data *sd =3D NULL;
> +	int init_mz =3D 0;
> +
> +	if (!name || !data)
> +		return -EINVAL;
> +
> +	/* name format is afu_?|??:??.? which is unique */
> +	snprintf(mz_name, sizeof(mz_name), "%s", name);
> +
> +	mz =3D rte_memzone_lookup(mz_name);
> +	if (!mz) {
> +		mz =3D rte_memzone_reserve(mz_name, sizeof(struct
> afu_shared_data),
> +				socket_id, 0);
> +		init_mz =3D 1;
> +	}
> +
> +	if (!mz) {
> +		IFPGA_RAWDEV_PMD_ERR("Allocate memory zone %s failed!",
> +			mz_name);
> +		return -ENOMEM;
> +	}
> +
> +	sd =3D (struct afu_shared_data *)mz->addr;
> +
> +	if (init_mz)  /* initialize memory zone on the first time */
> +		rte_spinlock_init(&sd->lock);
> +
> +	*data =3D sd;
> +
> +	return 0;
> +}
> +
> +static int afu_rawdev_name_get(struct rte_afu_device *afu_dev, char *nam=
e,
> +	size_t size)
> +{
> +	int n =3D 0;
> +
> +	if (!afu_dev || !name || !size)
> +		return -EINVAL;
> +
> +	n =3D snprintf(name, size, "afu_%s", afu_dev->device.name);
> +	if (n >=3D (int)size) {
> +		IFPGA_RAWDEV_PMD_ERR("Name of AFU device is too long!");
> +		return -ENAMETOOLONG;
> +	}
> +
> +	return 0;
> +}
> +
> +static struct afu_ops *afu_ops_get(struct rte_afu_uuid *afu_id) {
> +	struct afu_rawdev_drv *drv =3D NULL;
> +
> +	if (!afu_id)
> +		return NULL;
> +
> +	TAILQ_FOREACH(drv, &afu_pmd_list, next) {
> +		if ((drv->uuid.uuid_low =3D=3D afu_id->uuid_low) &&
> +			(drv->uuid.uuid_high =3D=3D afu_id->uuid_high))
> +			break;
> +	}
> +
> +	return drv ? drv->ops : NULL;
> +}
> +
> +static int afu_rawdev_create(struct rte_afu_device *afu_dev, int
> +socket_id) {
> +	struct rte_rawdev *rawdev =3D NULL;
> +	struct afu_rawdev *dev =3D NULL;
> +	char name[RTE_RAWDEV_NAME_MAX_LEN] =3D {0};
> +	int ret =3D 0;
> +
> +	if (!afu_dev)
> +		return -EINVAL;
> +
> +	ret =3D afu_rawdev_name_get(afu_dev, name, sizeof(name));
> +	if (ret)
> +		return ret;
> +
> +	IFPGA_RAWDEV_PMD_INFO("Create raw device %s on NUMA node
> %d",
> +		name, socket_id);
> +
> +	/* Allocate device structure */
> +	rawdev =3D rte_rawdev_pmd_allocate(name, sizeof(struct afu_rawdev),
> +				socket_id);
> +	if (!rawdev) {
> +		IFPGA_RAWDEV_PMD_ERR("Unable to allocate raw device");
> +		return -ENOMEM;
> +	}
> +
> +	rawdev->dev_ops =3D &afu_rawdev_ops;
> +	rawdev->device =3D &afu_dev->device;
> +	rawdev->driver_name =3D afu_dev->driver->driver.name;
> +
> +	dev =3D afu_rawdev_get_priv(rawdev);
> +	if (!dev)
> +		goto cleanup;
> +
> +	dev->rawdev =3D rawdev;
> +	dev->port =3D afu_dev->id.port;
> +	dev->addr =3D afu_dev->mem_resource[0].addr;
> +	dev->ops =3D afu_ops_get(&afu_dev->id.uuid);
> +	if (dev->ops =3D=3D NULL) {
> +		IFPGA_RAWDEV_PMD_ERR("Unsupported AFU device");
> +		goto cleanup;
> +	}
> +
> +	if (dev->ops->init) {
> +		ret =3D (*dev->ops->init)(dev);
> +		if (ret) {
> +			IFPGA_RAWDEV_PMD_ERR("Failed to init %s", name);
> +			goto cleanup;
> +		}
> +	}
> +
> +	ret =3D afu_shared_data_alloc(name, &dev->sd, socket_id);
> +	if (ret)
> +		goto cleanup;
> +
> +	return ret;
> +
> +cleanup:
> +	rte_rawdev_pmd_release(rawdev);
> +	return ret;
> +}
> +
> +static int afu_rawdev_destroy(struct rte_afu_device *afu_dev) {
> +	struct rte_rawdev *rawdev =3D NULL;
> +	char name[RTE_RAWDEV_NAME_MAX_LEN] =3D {0};
> +	int ret =3D 0;
> +
> +	if (!afu_dev)
> +		return -EINVAL;
> +
> +	ret =3D afu_rawdev_name_get(afu_dev, name, sizeof(name));
> +	if (ret)
> +		return ret;
> +
> +	IFPGA_RAWDEV_PMD_INFO("Destroy raw device %s", name);
> +
> +	rawdev =3D rte_rawdev_pmd_get_named_dev(name);
> +	if (!rawdev) {
> +		IFPGA_RAWDEV_PMD_ERR("Raw device %s not found", name);
> +		return -EINVAL;
> +	}
> +
> +	/* rte_rawdev_close is called by pmd_release */
> +	ret =3D rte_rawdev_pmd_release(rawdev);
> +	if (ret)
> +		IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
> +
> +	return 0;
> +}
> +
> +static int afu_rawdev_probe(struct rte_afu_device *afu_dev) {
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +	return afu_rawdev_create(afu_dev, rte_socket_id()); }
> +
> +static int afu_rawdev_remove(struct rte_afu_device *afu_dev) {
> +	IFPGA_RAWDEV_PMD_FUNC_TRACE();
> +	return afu_rawdev_destroy(afu_dev);
> +}
> +
> +static struct rte_afu_driver afu_pmd =3D {
> +	.id_table =3D afu_pmd_uuid_map,
> +	.probe =3D afu_rawdev_probe,
> +	.remove =3D afu_rawdev_remove
> +};
> +
> +RTE_PMD_REGISTER_AFU(afu_rawdev_driver, afu_pmd);
> +
> +static void update_uuid_map(void)
> +{
> +	int i =3D 0;
> +	struct rte_afu_uuid *afu_id =3D afu_pmd_uuid_map;
> +	struct afu_rawdev_drv *drv;
> +
> +	TAILQ_FOREACH(drv, &afu_pmd_list, next) {
> +		if (i++ < AFU_RAWDEV_MAX_DRVS) {
> +			afu_id->uuid_low =3D drv->uuid.uuid_low;
> +			afu_id->uuid_high =3D drv->uuid.uuid_high;
> +			afu_id++;
> +		}
> +	}
> +	if (i <=3D AFU_RAWDEV_MAX_DRVS) {
> +		afu_id->uuid_low =3D 0;
> +		afu_id->uuid_high =3D 0;
> +	}
> +}
> +
> +void afu_pmd_register(struct afu_rawdev_drv *driver) {
> +	TAILQ_INSERT_TAIL(&afu_pmd_list, driver, next);
> +	update_uuid_map();
> +}
> +
> +void afu_pmd_unregister(struct afu_rawdev_drv *driver) {
> +	TAILQ_REMOVE(&afu_pmd_list, driver, next);
> +	update_uuid_map();
> +}
> diff --git a/drivers/raw/ifpga/afu_pmd_core.h
> b/drivers/raw/ifpga/afu_pmd_core.h
> new file mode 100644
> index 0000000..4fad2c7
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_core.h
> @@ -0,0 +1,76 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright 2022 Intel Corporation
> + */
> +
> +#ifndef __AFU_PMD_CORE_H__
> +#define __AFU_PMD_CORE_H__
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <stdint.h>
> +#include <stdio.h>
> +#include <unistd.h>
> +
> +#include <rte_spinlock.h>
> +#include <rte_bus_ifpga.h>
> +#include <rte_rawdev.h>
> +
> +#include "ifpga_rawdev.h"
> +
> +#define AFU_RAWDEV_MAX_DRVS  32
> +
> +struct afu_rawdev;
> +
> +struct afu_ops {
> +	int (*init)(struct afu_rawdev *dev);
> +	int (*config)(struct afu_rawdev *dev, void *config,
> +		size_t config_size);
> +	int (*start)(struct afu_rawdev *dev);
> +	int (*stop)(struct afu_rawdev *dev);
> +	int (*test)(struct afu_rawdev *dev);
> +	int (*close)(struct afu_rawdev *dev);
> +	int (*reset)(struct afu_rawdev *dev);
> +	int (*dump)(struct afu_rawdev *dev, FILE *f); };
> +
> +struct afu_shared_data {
> +	rte_spinlock_t lock;  /* lock for multi-process access */ };
> +
> +struct afu_rawdev_drv {
> +	TAILQ_ENTRY(afu_rawdev_drv) next;
> +	struct rte_afu_uuid uuid;
> +	struct afu_ops *ops;
> +};
> +
> +struct afu_rawdev {
> +	struct rte_rawdev *rawdev;  /* point to parent raw device */
> +	struct afu_shared_data *sd;  /* shared data for multi-process */
> +	struct afu_ops *ops;  /* device operation functions */
> +	int port;  /* index of port the AFU attached */
> +	void *addr;  /* base address of AFU registers */
> +	void *priv;  /* private driver data */ };
> +
> +static inline struct afu_rawdev *
> +afu_rawdev_get_priv(const struct rte_rawdev *rawdev) {
> +	return rawdev ? (struct afu_rawdev *)rawdev->dev_private : NULL; }
> +
> +void afu_pmd_register(struct afu_rawdev_drv *driver); void
> +afu_pmd_unregister(struct afu_rawdev_drv *driver);
> +
> +#define AFU_PMD_REGISTER(drv)\
> +RTE_INIT(afupmdinitfunc_ ##drv)\
> +{\
> +	afu_pmd_register(&drv);\
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* __AFU_PMD_CORE_H__ */
> diff --git a/drivers/raw/ifpga/meson.build b/drivers/raw/ifpga/meson.buil=
d
> index aeccc17..d9a6f29 100644
> --- a/drivers/raw/ifpga/meson.build
> +++ b/drivers/raw/ifpga/meson.build
> @@ -13,7 +13,7 @@ objs =3D [base_objs]
>  deps +=3D ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvargs',
>      'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke']
>=20
> -sources =3D files('ifpga_rawdev.c', 'rte_pmd_ifpga.c')
> +sources =3D files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c')
>=20
>  includes +=3D include_directories('base')  includes +=3D
> include_directories('../../net/ipn3ke')
> --
> 1.8.3.1

It looks good for me, you can add:
Acked-by: Tianfei Zhang <tianfei.zhang@intel.com>