From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2B23A0557; Fri, 10 Jun 2022 08:12:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A529C40A7D; Fri, 10 Jun 2022 08:12:06 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 9ED1240221; Fri, 10 Jun 2022 08:12:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654841525; x=1686377525; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=wWJjFrlS3Avy1HqkFJuqDo4yVKEo5NCzJKInYj9jVnU=; b=KQcuDgzmeRsabvrMDNmZSCtR6o+uTn2vXH7xifDyFdySh0nP6Vvcu513 6d3I0hosnbCt5mCFW1R3KY/vkvaFTwocsDrCBmyCRERWqlPdycZwqCwHf NuLbEbVrOmEY0+wtGoXuAb49xDSEiGompHWX4osgLpDIeBvN9lhAihXNM iOM71DlOMco8RCKcVfEDAzZktRkgXHz1SQ9u0glP25uGRo7t8iOnMw+WH YkH9hmgF3IQQ0OLGcPUQFIcJLPOd823W+EwdD/QYK6KXay2HvuItNwjHp odsqetT3CKh/Akst6F6tCaVVrp3gv0JS4WiG51D47tHa1v037k32oLMYn w==; X-IronPort-AV: E=McAfee;i="6400,9594,10373"; a="260649033" X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="260649033" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2022 23:12:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,288,1647327600"; d="scan'208";a="671696701" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by FMSMGA003.fm.intel.com with ESMTP; 09 Jun 2022 23:12:03 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Thu, 9 Jun 2022 23:12:03 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Thu, 9 Jun 2022 23:12:02 -0700 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.170) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Thu, 9 Jun 2022 23:11:56 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D0UNPxD4SRZQTBr0/HNnkel5U5VoQSkbuBu7Ie3MwK9nynOF4gfbnV0/m98FKrj7awaqHleOGRxrnVnzrwroTxpj+pHtr6B1VOD6pOhui2keBrbc8bXpooXtH2XzOCWpEBlx0zwfZEcPxYi6iucREvNbEjAAYShLIRj92vpghwQ6+H0EnWTe34oFE+8rhVCWHL2JPKRJjmo+GKRJkIcnkBk5tmY8+q3EiciB7hRvn4NG79oL9DQZa7Es22By0GJrkSmdKesj9P4BlO86AEug0NL/LLWGAd6/tCjARBPScPO06egA4GpZJkoTBWHoPZGgMrVfbCL8YU6zrLYaHOPuGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1aHlLU1/mw//ajoJvHPjK90kcM04W2o9Gg5GNcLitno=; b=Irf4fob8mq+ZLEGV6bon9S1v9AxWLbF4oPKJ33PFI3e6YDF6Te+TbjGmfxI2fKMyV6cZKlP793ciibkCO22cobAMOtCoKURZIu2lBwNZSakVXy/pKsup4xo96A+PAb7SaCw5E2RHOu+w2yItnDuFFEd4UgF6m/uHUVyx/zC+gnEhfBnlmnwSzTDCOk01mXTJGbT9bie3+vXo18EFKk2PJqKzK/Vgik7a5ubfgyAwvZm1y58hdH8JxwkV52NQhXlDatSSedw4A5XZVTowm5nZ/jDwE3W1/jrg+8DVKUrKN+tgh/E8MoZir3xshU13gfjvtWnYIDsmdyuxRvee65Xhzw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from BL1PR11MB5477.namprd11.prod.outlook.com (2603:10b6:208:31f::19) by BL0PR11MB3233.namprd11.prod.outlook.com (2603:10b6:208:68::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.13; Fri, 10 Jun 2022 06:11:55 +0000 Received: from BL1PR11MB5477.namprd11.prod.outlook.com ([fe80::d866:27cd:1ae5:db2c]) by BL1PR11MB5477.namprd11.prod.outlook.com ([fe80::d866:27cd:1ae5:db2c%5]) with mapi id 15.20.5332.013; Fri, 10 Jun 2022 06:11:55 +0000 From: "Zhang, Tianfei" To: "Huang, Wei" , "dev@dpdk.org" , "thomas@monjalon.net" , "nipun.gupta@nxp.com" , "hemant.agrawal@nxp.com" CC: "stable@dpdk.org" , "Xu, Rosen" , "Zhang, Qi Z" Subject: RE: [PATCH v7 3/5] raw/ifpga: add HE-LPBK AFU driver Thread-Topic: [PATCH v7 3/5] raw/ifpga: add HE-LPBK AFU driver Thread-Index: AQHYe9K/4Ruq0KwrMEina0dENgED+K1IKkTg Date: Fri, 10 Jun 2022 06:11:55 +0000 Message-ID: References: <1654742650-7214-1-git-send-email-wei.huang@intel.com> <1654760242-7832-1-git-send-email-wei.huang@intel.com> <1654760242-7832-4-git-send-email-wei.huang@intel.com> In-Reply-To: <1654760242-7832-4-git-send-email-wei.huang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.500.17 dlp-reaction: no-action authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 50e7a66f-e943-44f9-054f-08da4aa81e92 x-ms-traffictypediagnostic: BL0PR11MB3233:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 2APmPYBJi4K+zW5Zu2G6p+DfBkyNtUMT+kdAw5LLtC5lfi6Zulx+VcIT/Jd8cPDiLOJ762p9RLhjOOERASTxeSsXiJX9MW0cdfwKtpzC4XBjd1o8M4Xe+U1tNhxkmAlHY8ZXbxydZ+hqoIx0nZ1Ons5okTLgTbD7oAGFB+DUKACHExwGDOcfyuNw3x/qXny0O9E4UVn2PVGOd42kVDsRNY0uXTqUxqi8R1Wz6/htK939y1J5B5mI4vn2nHoBUfd3RYeUsk1nwK1K6elq2XXcoltPoallSt2B+ewfnMj9R6v9+3O6RFXOBD4NQpXD1E01JLln2wqtmSxgUjKVk2XloYe+HHE/uG1ny7V3661QHQa8Dzbck+Z0dxWXBhAhyTrg1Ftw58v+a6xHDfOUHioy4K1GKo3LP7Hq3i15P/y5PKPP2KMRMYUft1t7i6h4F0XzAFRdxo/W4z0r2dGp7DyPl3MBasu1tKQ8Ew1iJ0g6eOsJYJnFvv3iwHmviPqk8AuD4NszZ8K3oQyp/tFPDaGsz8+emzAYq7Q3CFJhlE6Hr3OWa5Qh3CnFnyw4ZvyEXunV13LEOQdOL9mEewYQq0UNFVLo2zGLP4oxfFaK7DTqFCu4ApeJvZm6XokriIEpIBe+97PoxVIvrBVOrQiBhRzYdRUeKw0wSUBlMqXXoulDQkokwfTLIGJlmRxOcwL2FS98f+Abak2WMenQQ7mo+Jeh2g== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BL1PR11MB5477.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(366004)(508600001)(86362001)(2906002)(8676002)(4326008)(122000001)(38100700002)(38070700005)(316002)(66446008)(64756008)(66946007)(66476007)(66556008)(76116006)(82960400001)(55016003)(8936002)(52536014)(54906003)(71200400001)(30864003)(110136005)(5660300002)(33656002)(83380400001)(7696005)(6506007)(53546011)(186003)(107886003)(9686003)(579004); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 2 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?+2vwUb4HoIp4juUGyrKq8T4mLVaQtWA//np7LX6s2KPK7c/f7CVE780Va5Dk?= =?us-ascii?Q?1HmJIxX+L+DmlDSpR/QV+qcxw51LosDubtRCCX8IaVUYa3QAlNojqBn2uzEo?= =?us-ascii?Q?50iFNRfggKo+lnTBN3D4QoTXWnaZ88XUI5BlTTWpKbzZKjqttiXOh4shTlqy?= =?us-ascii?Q?0ZGaAqvUbxZCZ/kFHmY8g3+2os4UavWrKEghh0PIFGgRO16nj9D9g7IGhgbe?= =?us-ascii?Q?DG65cKLlvxTcT2xRHVVOZgFb67NRywecBTWngr7aof7W+jgLS0NFWtl6kkrx?= =?us-ascii?Q?D+wOuM6RMb3AxLsI8ZKdm7uvFsbjQoYnVDYy/cS59y854hMAtln6K/vCaQIO?= =?us-ascii?Q?6br2f/HKOiNFNZe8ak9rDVNWj/gliNgPAF9SLHHbXEpr5j/WXQbOSgK0aco1?= =?us-ascii?Q?h9NwTNXnw3RC7AH7r22K2F5ebn4dRy1L77xth1joeFjTvjHWVo1KA1LxGUtZ?= =?us-ascii?Q?2+TitMk+V7fsK88qeCJ4QRt/ngd3B/2w7/jjpLuGQeXHS6uw/5+xORuwX6UP?= =?us-ascii?Q?P+vQUxjydwGeqBw2p3pQt0kDUEF2Xi6OTcFDxUmIe2ZD1RVPOq9J7Fi3/jok?= =?us-ascii?Q?gFmkKtvZXYPg2q6YdNGDJpF9j9+DH8mUiFZD5Qe5GkUVdxJHQHgsCEzEEnQG?= =?us-ascii?Q?l5iFR5whFXff5xGSRvVDb6gwML+v0CfMqEfiCc0W14RrtcoPti0LvD55SI/U?= =?us-ascii?Q?3yv+LAb3qiWoFMocF71hYewITYO7d4iftBd/DgtyOXbfC7l5qXppQZElTISI?= =?us-ascii?Q?fExU1gUkD9R4L7SnT1FYTrKIVEz3Gdjr9BqWqIGQnfGUViPQR4NyI6wqOOZB?= =?us-ascii?Q?G1NSTP1aRoRIgslzKlXAMVWbIUMs0EIfd67p4THX9jUu/nlyFEbvfbq6mdKB?= =?us-ascii?Q?5+/rATHb0cTvZRvZ3siKQXmn3+Mc4zZAcaxtfUfslzNyT90gNpLQwnL2EZ4F?= =?us-ascii?Q?6TSEfL36J1Or/tu+2sODIi5TDbQENW9BPzU8qTNaYYWlgfLE1Cp3EFe/lVMF?= =?us-ascii?Q?SG+g74bSKqDZYg/0lAcLdHhlEsz08XW0yLb2BlIyIDkLz0m+P53CbUJZb+sD?= =?us-ascii?Q?rTYWBJJnYbP5EhVbwLaf34zGnV1kKcDZCc0jZmegDY4XpFBZtAFDYPEjV7Bj?= =?us-ascii?Q?rtURN641EBrMeHWx/44+p/GE+DlZ/VYhXA+uHN8b59FGdOfkg93zK6KT/j1i?= =?us-ascii?Q?GNHi/RmYAdHHvH4bG6sGxmyvN+fZSH2vusyOW4z0TWp0S3RdEe9/XBPrlx4b?= =?us-ascii?Q?Hb1PMi3LWSSehTUxSvmp+JTwato8RWi3LJV+AgTkxO017q9bAU/yCOmd8Ra9?= =?us-ascii?Q?jqW/k3BjVkbX9QAEib3sSlgEpD8QzcVPTDvF7pHLJqd4Sr8fgvu8s3VahbpF?= =?us-ascii?Q?bUzGGKM5Qtcwsw89G17ySfTCBLsqVNQiAb/wPTbMbDJMOYrZ6YQZZ89X2bvG?= =?us-ascii?Q?u+lLE7IPx3Z4eSWOuipXqH3AytS3gqqI67XzU1MTF0klhElDJqPm6AiLv5Kv?= =?us-ascii?Q?3lyR9KgnY6BxRBjDN+/MvPg7Tm38AaYUl1jrLA4Ko3R4LoVoy89Hy6axJHL6?= =?us-ascii?Q?sqB/seEZwpUs2YZ+UAAChGK7JWUTxMgbm6B/PtaIheD1lX9c+lvV3FbODkdt?= =?us-ascii?Q?fY9ZzVArc9PU0MhbldkkI2PK2Zhvx7/NQ8hk2pygyfCG18FKJZcOfRlwHGwQ?= =?us-ascii?Q?yKpS0PC2EYmm9yKEdFuxV1zXdWxHBb8ltgcM/l/NG3lahSh1Dzp8SbNzP/sZ?= =?us-ascii?Q?BwhP64OlKUUEdGkDsRMVvYBKLqFREYbA1ff38LgIGN0rgZDpXrTaBQIqvPHo?= x-ms-exchange-antispam-messagedata-1: RzIP894KMubo1BniHaykdGvpUEdP/6tgTXg= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR11MB5477.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 50e7a66f-e943-44f9-054f-08da4aa81e92 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jun 2022 06:11:55.3881 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Vqel5BuhtmKBFXO/O9lj5qFXtWGRm1rhJHsfmtdXURDU7clhA0bCNsxV3k337kHQi0u6N8aIir8cTFGRCJ2X2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR11MB3233 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Huang, Wei > Sent: Thursday, June 9, 2022 3:37 PM > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com; > hemant.agrawal@nxp.com > Cc: stable@dpdk.org; Xu, Rosen ; Zhang, Tianfei > ; Zhang, Qi Z ; Huang, Wei > > Subject: [PATCH v7 3/5] raw/ifpga: add HE-LPBK AFU driver >=20 > HE-LPBK and HE-MEM-LPBK are host exerciser modules in OFS FPGA, HE-LPBK i= s > used to test PCI bus and HE-MEM-LPBK is used to test local memory. > This driver initialize the modules and report test result. >=20 > Signed-off-by: Wei Huang > --- > v2: move source files to ifpga and rename, refine code > --- > drivers/raw/ifpga/afu_pmd_he_lpbk.c | 436 > ++++++++++++++++++++++++++++++++++++ > drivers/raw/ifpga/afu_pmd_he_lpbk.h | 126 +++++++++++ > drivers/raw/ifpga/meson.build | 2 +- > drivers/raw/ifpga/rte_pmd_afu.h | 14 ++ > 4 files changed, 577 insertions(+), 1 deletion(-) create mode 100644 > drivers/raw/ifpga/afu_pmd_he_lpbk.c > create mode 100644 drivers/raw/ifpga/afu_pmd_he_lpbk.h >=20 > diff --git a/drivers/raw/ifpga/afu_pmd_he_lpbk.c > b/drivers/raw/ifpga/afu_pmd_he_lpbk.c > new file mode 100644 > index 0000000..8b2c85b > --- /dev/null > +++ b/drivers/raw/ifpga/afu_pmd_he_lpbk.c > @@ -0,0 +1,436 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Intel Corporation > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "afu_pmd_core.h" > +#include "afu_pmd_he_lpbk.h" > + > +static int he_lpbk_afu_config(struct afu_rawdev *dev) { > + struct he_lpbk_priv *priv =3D NULL; > + struct rte_pmd_afu_he_lpbk_cfg *cfg =3D NULL; > + struct he_lpbk_csr_cfg v; > + > + if (!dev) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + cfg =3D &priv->he_lpbk_cfg; > + > + v.csr =3D 0; > + > + if (cfg->cont) > + v.cont =3D 1; > + > + v.mode =3D cfg->mode; > + v.trput_interleave =3D cfg->trput_interleave; > + if (cfg->multi_cl =3D=3D 4) > + v.multicl_len =3D 2; > + else > + v.multicl_len =3D cfg->multi_cl - 1; > + > + IFPGA_RAWDEV_PMD_DEBUG("cfg: 0x%08x", v.csr); > + rte_write32(v.csr, priv->he_lpbk_ctx.addr + CSR_CFG); > + > + return 0; > +} > + > +static void he_lpbk_report(struct afu_rawdev *dev, uint32_t cl) { > + struct he_lpbk_priv *priv =3D NULL; > + struct rte_pmd_afu_he_lpbk_cfg *cfg =3D NULL; > + struct he_lpbk_ctx *ctx =3D NULL; > + struct he_lpbk_dsm_status *stat =3D NULL; > + struct he_lpbk_status0 stat0; > + struct he_lpbk_status1 stat1; > + uint64_t swtest_msg =3D 0; > + uint64_t ticks =3D 0; > + uint64_t info =3D 0; > + double num, rd_bw, wr_bw; > + > + if (!dev || !dev->priv) > + return; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + cfg =3D &priv->he_lpbk_cfg; > + ctx =3D &priv->he_lpbk_ctx; > + > + stat =3D ctx->status_ptr; > + > + swtest_msg =3D rte_read64(ctx->addr + CSR_SWTEST_MSG); > + stat0.csr =3D rte_read64(ctx->addr + CSR_STATUS0); > + stat1.csr =3D rte_read64(ctx->addr + CSR_STATUS1); > + > + if (cfg->cont) > + ticks =3D stat->num_clocks - stat->start_overhead; > + else > + ticks =3D stat->num_clocks - > + (stat->start_overhead + stat->end_overhead); > + > + if (cfg->freq_mhz =3D=3D 0) { > + info =3D rte_read64(ctx->addr + CSR_HE_INFO0); > + IFPGA_RAWDEV_PMD_INFO("API version: %"PRIx64, info >> > 16); > + cfg->freq_mhz =3D info & 0xffff; > + if (cfg->freq_mhz =3D=3D 0) { > + IFPGA_RAWDEV_PMD_INFO("Frequency of AFU clock is > unknown." > + " Assuming 350 MHz."); > + cfg->freq_mhz =3D 350; > + } > + } > + > + num =3D (double)stat0.num_reads; > + rd_bw =3D (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks; > + num =3D (double)stat0.num_writes; > + wr_bw =3D (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks; > + > + printf("Cachelines Read_Count Write_Count Pend_Read Pend_Write " > + "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n", > + cfg->freq_mhz); > + printf("%10u %10u %10u %10u %10u %12"PRIu64 > + " %7.3f GB/s %7.3f GB/s\n", > + cl, stat0.num_reads, stat0.num_writes, > + stat1.num_pend_reads, stat1.num_pend_writes, > + ticks, rd_bw / 1e9, wr_bw / 1e9); > + printf("Test Message: 0x%"PRIx64"\n", swtest_msg); } > + > +static int he_lpbk_test(struct afu_rawdev *dev) { > + struct he_lpbk_priv *priv =3D NULL; > + struct rte_pmd_afu_he_lpbk_cfg *cfg =3D NULL; > + struct he_lpbk_ctx *ctx =3D NULL; > + struct he_lpbk_csr_ctl ctl; > + uint32_t *ptr =3D NULL; > + uint32_t i, j, cl, val =3D 0; > + uint64_t sval =3D 0; > + int ret =3D 0; > + > + if (!dev) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + cfg =3D &priv->he_lpbk_cfg; > + ctx =3D &priv->he_lpbk_ctx; > + > + ctl.csr =3D 0; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + rte_delay_us(1000); > + ctl.reset =3D 1; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + > + /* initialize DMA addresses */ > + IFPGA_RAWDEV_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova); > + rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + CSR_SRC_ADDR); > + > + IFPGA_RAWDEV_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova); > + rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + CSR_DST_ADDR); > + > + IFPGA_RAWDEV_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx- > >dsm_iova); > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr + > CSR_AFU_DSM_BASEL); > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32, > + ctx->addr + CSR_AFU_DSM_BASEH); > + > + ret =3D he_lpbk_afu_config(dev); > + if (ret) > + return ret; > + > + /* initialize src data */ > + ptr =3D (uint32_t *)ctx->src_ptr; > + j =3D CLS_TO_SIZE(cfg->end) >> 2; > + for (i =3D 0; i < j; i++) > + *ptr++ =3D i; > + > + /* start test */ > + for (cl =3D cfg->begin; cl <=3D cfg->end; cl +=3D cfg->multi_cl) { > + memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl)); > + memset(ctx->dsm_ptr, 0, DSM_SIZE); > + > + ctl.csr =3D 0; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + rte_delay_us(1000); > + ctl.reset =3D 1; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + > + rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES); > + > + ctl.start =3D 1; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + > + if (cfg->cont) { > + rte_delay_ms(cfg->timeout * 1000); > + ctl.force_completion =3D 1; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + ret =3D dsm_poll_timeout(&ctx->status_ptr- > >test_complete, > + val, (val & 0x1) =3D=3D 1, DSM_POLL_INTERVAL, > + DSM_TIMEOUT); > + if (ret) { > + printf("DSM poll timeout\n"); > + goto end; > + } > + } else { > + ret =3D dsm_poll_timeout(&ctx->status_ptr- > >test_complete, > + val, (val & 0x1) =3D=3D 1, DSM_POLL_INTERVAL, > + DSM_TIMEOUT); > + if (ret) { > + printf("DSM poll timeout\n"); > + goto end; > + } > + ctl.force_completion =3D 1; > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > + } > + > + he_lpbk_report(dev, cl); > + > + i =3D 0; > + while (i++ < 100) { > + sval =3D rte_read64(ctx->addr + CSR_STATUS1); > + if (sval =3D=3D 0) > + break; > + rte_delay_us(1000); > + } > + > + if (cfg->mode =3D=3D NLB_MODE_LPBK) { > + ptr =3D (uint32_t *)ctx->dest_ptr; > + j =3D CLS_TO_SIZE(cl) >> 2; > + for (i =3D 0; i < j; i++) { > + if (*ptr++ !=3D i) { > + IFPGA_RAWDEV_PMD_ERR("Data > mismatch @ %u", i); > + break; > + } > + } > + } > + } > + > +end: > + return 0; > +} > + > +static int he_lpbk_ctx_release(struct afu_rawdev *dev) { > + struct he_lpbk_priv *priv =3D NULL; > + struct he_lpbk_ctx *ctx =3D NULL; > + > + if (!dev) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + ctx =3D &priv->he_lpbk_ctx; > + > + rte_free(ctx->dsm_ptr); > + ctx->dsm_ptr =3D NULL; > + ctx->status_ptr =3D NULL; > + > + rte_free(ctx->src_ptr); > + ctx->src_ptr =3D NULL; > + > + rte_free(ctx->dest_ptr); > + ctx->dest_ptr =3D NULL; > + > + return 0; > +} > + > +static int he_lpbk_ctx_init(struct afu_rawdev *dev) { > + struct he_lpbk_priv *priv =3D NULL; > + struct he_lpbk_ctx *ctx =3D NULL; > + int ret =3D 0; > + > + if (!dev) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + ctx =3D &priv->he_lpbk_ctx; > + ctx->addr =3D (uint8_t *)dev->addr; > + > + ctx->dsm_ptr =3D (uint8_t *)rte_zmalloc(NULL, DSM_SIZE, > TEST_MEM_ALIGN); > + if (!ctx->dsm_ptr) > + return -ENOMEM; > + ctx->dsm_iova =3D rte_malloc_virt2iova(ctx->dsm_ptr); > + if (ctx->dsm_iova =3D=3D RTE_BAD_IOVA) { > + ret =3D -ENOMEM; > + goto release_dsm; > + } > + > + ctx->src_ptr =3D (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE, > + TEST_MEM_ALIGN); > + if (!ctx->src_ptr) { > + ret =3D -ENOMEM; > + goto release_dsm; > + } > + ctx->src_iova =3D rte_malloc_virt2iova(ctx->src_ptr); > + if (ctx->src_iova =3D=3D RTE_BAD_IOVA) { > + ret =3D -ENOMEM; > + goto release_src; > + } > + > + ctx->dest_ptr =3D (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE, > + TEST_MEM_ALIGN); > + if (!ctx->dest_ptr) { > + ret =3D -ENOMEM; > + goto release_src; > + } > + ctx->dest_iova =3D rte_malloc_virt2iova(ctx->dest_ptr); > + if (ctx->dest_iova =3D=3D RTE_BAD_IOVA) { > + ret =3D -ENOMEM; > + goto release_dest; > + } > + > + ctx->status_ptr =3D (struct he_lpbk_dsm_status *)ctx->dsm_ptr; > + return 0; > + > +release_dest: > + rte_free(ctx->dest_ptr); > + ctx->dest_ptr =3D NULL; > +release_src: > + rte_free(ctx->src_ptr); > + ctx->src_ptr =3D NULL; > +release_dsm: > + rte_free(ctx->dsm_ptr); > + ctx->dsm_ptr =3D NULL; > + return ret; > +} > + > +static int he_lpbk_init(struct afu_rawdev *dev) { > + if (!dev) > + return -EINVAL; > + > + if (!dev->priv) { > + dev->priv =3D rte_zmalloc(NULL, sizeof(struct he_lpbk_priv), 0); > + if (!dev->priv) > + return -ENOMEM; > + } > + > + return he_lpbk_ctx_init(dev); > +} > + > +static int he_lpbk_config(struct afu_rawdev *dev, void *config, > + size_t config_size) > +{ > + struct he_lpbk_priv *priv =3D NULL; > + struct rte_pmd_afu_he_lpbk_cfg *cfg =3D NULL; > + > + if (!dev || !config || !config_size) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + if (config_size !=3D sizeof(struct rte_pmd_afu_he_lpbk_cfg)) > + return -EINVAL; > + > + cfg =3D (struct rte_pmd_afu_he_lpbk_cfg *)config; > + if (cfg->mode > NLB_MODE_TRPUT) > + return -EINVAL; > + if ((cfg->multi_cl !=3D 1) && (cfg->multi_cl !=3D 2) && > + (cfg->multi_cl !=3D 4)) > + return -EINVAL; > + if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin > > MAX_CACHE_LINES)) > + return -EINVAL; > + if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES)) > + return -EINVAL; > + > + rte_memcpy(&priv->he_lpbk_cfg, cfg, sizeof(priv->he_lpbk_cfg)); > + > + return 0; > +} > + > +static int he_lpbk_close(struct afu_rawdev *dev) { > + if (!dev) > + return -EINVAL; > + > + he_lpbk_ctx_release(dev); > + > + rte_free(dev->priv); > + dev->priv =3D NULL; > + > + return 0; > +} > + > +static int he_lpbk_dump(struct afu_rawdev *dev, FILE *f) { > + struct he_lpbk_priv *priv =3D NULL; > + struct he_lpbk_ctx *ctx =3D NULL; > + > + if (!dev) > + return -EINVAL; > + > + priv =3D (struct he_lpbk_priv *)dev->priv; > + if (!priv) > + return -ENOENT; > + > + if (!f) > + f =3D stdout; > + > + ctx =3D &priv->he_lpbk_ctx; > + > + fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr); > + fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr); > + fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova); > + fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr); > + fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova); > + fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr); > + fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova); > + fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr); > + > + return 0; > +} > + > +static struct afu_ops he_lpbk_ops =3D { > + .init =3D he_lpbk_init, > + .config =3D he_lpbk_config, > + .start =3D NULL, > + .stop =3D NULL, > + .test =3D he_lpbk_test, > + .close =3D he_lpbk_close, > + .dump =3D he_lpbk_dump, > + .reset =3D NULL > +}; > + > +struct afu_rawdev_drv he_lpbk_drv =3D { > + .uuid =3D { HE_LPBK_UUID_L, HE_LPBK_UUID_H }, > + .ops =3D &he_lpbk_ops > +}; > + > +AFU_PMD_REGISTER(he_lpbk_drv); > + > +struct afu_rawdev_drv he_mem_lpbk_drv =3D { > + .uuid =3D { HE_MEM_LPBK_UUID_L, HE_MEM_LPBK_UUID_H }, > + .ops =3D &he_lpbk_ops > +}; > + > +AFU_PMD_REGISTER(he_mem_lpbk_drv); > diff --git a/drivers/raw/ifpga/afu_pmd_he_lpbk.h > b/drivers/raw/ifpga/afu_pmd_he_lpbk.h > new file mode 100644 > index 0000000..5ad6aa8 > --- /dev/null > +++ b/drivers/raw/ifpga/afu_pmd_he_lpbk.h > @@ -0,0 +1,126 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2022 Intel Corporation > + */ > + > +#ifndef _AFU_PMD_HE_LPBK_H_ > +#define _AFU_PMD_HE_LPBK_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "afu_pmd_core.h" > +#include "rte_pmd_afu.h" > + > +#define HE_LPBK_UUID_L 0xb94b12284c31e02b > +#define HE_LPBK_UUID_H 0x56e203e9864f49a7 > +#define HE_MEM_LPBK_UUID_L 0xbb652a578330a8eb #define > +HE_MEM_LPBK_UUID_H 0x8568ab4e6ba54616 > + > +/* HE-LBK & HE-MEM-LBK registers definition */ > +#define CSR_SCRATCHPAD0 0x100 > +#define CSR_SCRATCHPAD1 0x108 > +#define CSR_AFU_DSM_BASEL 0x110 > +#define CSR_AFU_DSM_BASEH 0x114 > +#define CSR_SRC_ADDR 0x120 > +#define CSR_DST_ADDR 0x128 > +#define CSR_NUM_LINES 0x130 > +#define CSR_CTL 0x138 > +#define CSR_CFG 0x140 > +#define CSR_INACT_THRESH 0x148 > +#define CSR_INTERRUPT0 0x150 > +#define CSR_SWTEST_MSG 0x158 > +#define CSR_STATUS0 0x160 > +#define CSR_STATUS1 0x168 > +#define CSR_ERROR 0x170 > +#define CSR_STRIDE 0x178 > +#define CSR_HE_INFO0 0x180 > + > +#define DSM_SIZE 0x200000 > +#define DSM_POLL_INTERVAL 5 /* ms */ > +#define DSM_TIMEOUT 1000 /* ms */ > + > +#define NLB_BUF_SIZE 0x400000 > +#define TEST_MEM_ALIGN 1024 > + > +struct he_lpbk_csr_ctl { > + union { > + uint32_t csr; > + struct { > + uint32_t reset:1; > + uint32_t start:1; > + uint32_t force_completion:1; > + uint32_t reserved:29; > + }; > + }; > +}; > + > +struct he_lpbk_csr_cfg { > + union { > + uint32_t csr; > + struct { > + uint32_t rsvd1:1; > + uint32_t cont:1; > + uint32_t mode:3; > + uint32_t multicl_len:2; > + uint32_t rsvd2:13; > + uint32_t trput_interleave:3; > + uint32_t test_cfg:5; > + uint32_t interrupt_on_error:1; > + uint32_t interrupt_testmode:1; > + uint32_t rsvd3:2; > + }; > + }; > +}; > + > +struct he_lpbk_status0 { > + union { > + uint64_t csr; > + struct { > + uint32_t num_writes; > + uint32_t num_reads; > + }; > + }; > +}; > + > +struct he_lpbk_status1 { > + union { > + uint64_t csr; > + struct { > + uint32_t num_pend_writes; > + uint32_t num_pend_reads; > + }; > + }; > +}; > + > +struct he_lpbk_dsm_status { > + uint32_t test_complete; > + uint32_t test_error; > + uint64_t num_clocks; > + uint32_t num_reads; > + uint32_t num_writes; > + uint32_t start_overhead; > + uint32_t end_overhead; > +}; > + > +struct he_lpbk_ctx { > + uint8_t *addr; > + uint8_t *dsm_ptr; > + uint64_t dsm_iova; > + uint8_t *src_ptr; > + uint64_t src_iova; > + uint8_t *dest_ptr; > + uint64_t dest_iova; > + struct he_lpbk_dsm_status *status_ptr; }; > + > +struct he_lpbk_priv { > + struct rte_pmd_afu_he_lpbk_cfg he_lpbk_cfg; > + struct he_lpbk_ctx he_lpbk_ctx; > +}; > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _AFU_PMD_HE_LPBK_H_ */ > diff --git a/drivers/raw/ifpga/meson.build b/drivers/raw/ifpga/meson.buil= d > index 2294ab5..629ff8a 100644 > --- a/drivers/raw/ifpga/meson.build > +++ b/drivers/raw/ifpga/meson.build > @@ -14,7 +14,7 @@ deps +=3D ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvarg= s', > 'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke'] >=20 > sources =3D files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c', > - 'afu_pmd_n3000.c') > + 'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c') >=20 > includes +=3D include_directories('base') includes +=3D > include_directories('../../net/ipn3ke') > diff --git a/drivers/raw/ifpga/rte_pmd_afu.h b/drivers/raw/ifpga/rte_pmd_= afu.h > index f14a053..19b3902 100644 > --- a/drivers/raw/ifpga/rte_pmd_afu.h > +++ b/drivers/raw/ifpga/rte_pmd_afu.h > @@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg { > }; > }; >=20 > +/** > + * HE-LPBK & HE-MEM-LPBK AFU configuration data structure. > + */ > +struct rte_pmd_afu_he_lpbk_cfg { > + uint32_t mode; > + uint32_t begin; > + uint32_t end; > + uint32_t multi_cl; > + uint32_t cont; > + uint32_t timeout; > + uint32_t trput_interleave; > + uint32_t freq_mhz; > +}; > + > #ifdef __cplusplus > } > #endif > -- It looks good for me, you can add: Acked-by: Tianfei Zhang