From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from BLU004-OMC2S1.hotmail.com (blu004-omc2s1.hotmail.com [65.55.111.76]) by dpdk.org (Postfix) with ESMTP id 075BBADA7 for ; Thu, 16 Apr 2015 13:29:27 +0200 (CEST) Received: from BLU436-SMTP243 ([65.55.111.71]) by BLU004-OMC2S1.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Thu, 16 Apr 2015 04:29:27 -0700 X-TMN: [nX8fljmjlTAFfJHu1xhPkxeWhSFL8sMM] X-Originating-Email: [dong.wang.pro@hotmail.com] Message-ID: Date: Thu, 16 Apr 2015 19:29:21 +0800 From: Wang Dong User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Stephen Hemminger References: <2601191342CEEE43887BDE71AB97725821415A3A@irsmsx105.ger.corp.intel.com> <20150415090642.0137f4c9@urahara> In-Reply-To: <20150415090642.0137f4c9@urahara> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 16 Apr 2015 11:29:27.0072 (UTC) FILETIME=[98CB8200:01D07838] Sender: Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH] ixgbe:Add write memory barrier for recv pkts. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Apr 2015 11:29:28 -0000 > On Wed, 15 Apr 2015 21:46:27 +0800 > Dong.Wang wrote: > >> Yes, current implementation works well with IA, and the transmit packets >> function's rte_wmb() is also unneccessary. >> >> But there are two reasons for adding rte_wmb() in recv pkts function: >> 1) The memory barrier in recv pkts function and xmit pkts function are >> inconsistent, rte_wmb() should be added to recv pkts function or be >> removed from xmit pkts function. >> 2) DPDK will support PowerPC processor (Other developers are working on >> it), I check the memory ordering of PowerPC, there was no mention of >> store-store instruction's principle in MPC8544 Reference Manual, only >> said it is weak memory ordering. >> >> So, I think it is neccessary to add rte_wmb() to recv pkts function. >> >> Dong > > If PowerPC requires additional memory barriers then it should > introduce a new generic set of memory barrier macros that are no-ops > on other architectures. > > Please don't penalize x86 for places where other CPU's have > weaker consistency. > Yes, put rte_wmb() here will penalize x86, I was inconsiderate of it. Maybe a new set of memory barrier macros will be introduced, it be discussed in another thread. For now, add rte_wmb() is unnessary, I'm waiting for new memory barrier macros. Dong