From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from BLU004-OMC4S18.hotmail.com (blu004-omc4s18.hotmail.com [65.55.111.157]) by dpdk.org (Postfix) with ESMTP id 9FFEDC358 for ; Sun, 28 Jun 2015 17:19:20 +0200 (CEST) Received: from BLU437-SMTP8 ([65.55.111.135]) by BLU004-OMC4S18.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Sun, 28 Jun 2015 08:19:20 -0700 X-TMN: [SjjUbW24t68jk2u4RZhog15cesNP+Rdo] X-Originating-Email: [dong.wang.pro@hotmail.com] Message-ID: From: WangDong To: dev@dpdk.org Date: Sun, 28 Jun 2015 23:19:03 +0800 X-Mailer: git-send-email 2.1.0 X-OriginalArrivalTime: 28 Jun 2015 15:19:19.0482 (UTC) FILETIME=[CDDE01A0:01D0B1B5] MIME-Version: 1.0 Content-Type: text/plain Subject: [dpdk-dev] [PATCH 1/2] eal:Introduce rte_dma_wmb/rte_dma_rmb. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Jun 2015 15:19:21 -0000 These macro can be used to replace current PMD's compiler memory barrier (volatile varible) and rte_wmb. In x86, they implement to compiler memory barrier. In power, they implement to processor memory barrier. --- .../common/include/arch/ppc_64/rte_atomic.h | 4 ++++ .../common/include/arch/x86/rte_atomic.h | 4 ++++ lib/librte_eal/common/include/generic/rte_atomic.h | 25 ++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index fb7af2b..8f4129d 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -72,6 +72,10 @@ extern "C" { */ #define rte_rmb() {asm volatile("sync" : : : "memory"); } +#define rte_dma_wmb() {asm volatile("sync" : : : "memory"); } + +#define rte_dma_rmb() {asm volatile("sync" : : : "memory"); + /*------------------------- 16 bit atomic operations -------------------------*/ /* To be compatible with Power7, use GCC built-in functions for 16 bit * operations */ diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h index e93e8ee..7cfbe8f 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h @@ -53,6 +53,10 @@ extern "C" { #define rte_rmb() _mm_lfence() +#define rte_dma_wmb() rte_compiler_barrier() + +#define rte_dma_rmb() rte_compiler_barrier() + /*------------------------- 16 bit atomic operations -------------------------*/ #ifndef RTE_FORCE_INTRINSICS diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h index 6c7581a..a51eeee 100644 --- a/lib/librte_eal/common/include/generic/rte_atomic.h +++ b/lib/librte_eal/common/include/generic/rte_atomic.h @@ -72,6 +72,31 @@ static inline void rte_wmb(void); */ static inline void rte_rmb(void); +/** + * Write memory barrier for DMA. + * + * Be used in PMD, unlike rte_wmb() which use processor memory barrier, + * this memory barrier focus on performance, if compiler memory barrier + * is sufficient for guarantee memory ordering, this function will + * use compiler memory barrier. + * + * This function is architecture dependent. + */ +static inline void rte_dma_wmb(void); + +/** + * Read memory barrier for DMA. + * + * Be used in PMD, unlike rte_rmb() which use processor memory barrier, + * this memory barrier focus on performance, if compiler memory barrier + * is sufficient for guarantee memory ordering, this function will + * use compiler memory barrier. + * + * This function is architecture dependent. + */ +static inline void rte_dma_rmb(void); + + #endif /* __DOXYGEN__ */ /** -- 2.1.0