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Fri, 23 Dec 2016 19:18:37 +0000 From: "Mody, Rasesh" To: Ferruh Yigit , "dev@dpdk.org" CC: Dept-Eng DPDK Dev Thread-Topic: [dpdk-dev] [PATCH 20/25] net/qede: add PCI ids for new chip variant Thread-Index: AQHSTUVg+FTegcjF9kSWScuL0r+rcaEVyvMAgAA8fDA= Date: Fri, 23 Dec 2016 19:18:36 +0000 Message-ID: References: <1480756289-11835-1-git-send-email-Rasesh.Mody@cavium.com> <1480756289-11835-21-git-send-email-Rasesh.Mody@cavium.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasesh.Mody@cavium.com; x-originating-ip: [2601:646:8180:be50:cdea:60f4:360a:6d99] x-ms-office365-filtering-correlation-id: 5df8b419-92e5-410b-6f07-08d42b687edb x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:BLUPR0701MB1569; x-microsoft-exchange-diagnostics: 1; BLUPR0701MB1569; 7:ARAj66fgq5kGZVWWFcUJosKL+E22yUr3F95t+Ybemjt35GlkLzGcTMc2Eo2hAA1yD6PP57oo1CxdV9aeB5jS3U0Wwc0MNK4gwkxGb/G21gXPYFjLke/eiF7ukwUKlYnv72acrYk6OW/2NBGrOMpWvTcgzHEjhuT99pkjxhhbykTvHounOTGdUvWNBcMqSOjwywsqtvY2RxvO2tC9d+Odo8s/KopHIzczPypicAdu6VeTlB2nOzztKDGMh3gN1xYOulg/SqIthcDe7yTxMnz+KM77W3nv/qH07YucR8Yp1dNSYdaLhnJsuNS1ArCp8PtRLAakysncSNXlqU0UluTv0dI7f/CPLPtXwhqPFcJ6yDUutV+H522PBfqjLfpNZXZef0p0FgaTM7AmCKJ1epYm9M8/B7WOvjHFHjDhcGafMHnQSFVnkeDsZ9MJnqqcUYxs/myLGq+y5/VigaWxF+Rqxw== x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(228905959029699); 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FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Dec 2016 19:18:36.7302 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1569 Subject: Re: [dpdk-dev] [PATCH 20/25] net/qede: add PCI ids for new chip variant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Dec 2016 19:18:43 -0000 > From: Ferruh Yigit [mailto:ferruh.yigit@intel.com] > Sent: Friday, December 23, 2016 7:39 AM >=20 > On 12/3/2016 9:11 AM, Rasesh Mody wrote: > > Add PCI IDs for new asic type (defined as CHIP_NUM_AH_xxx). > > It supports 50G, 40G, 25G and 10G speeds. > > > > Signed-off-by: Rasesh Mody > > --- > > drivers/net/qede/base/ecore_dev.c | 7 +++++- > > drivers/net/qede/qede_ethdev.c | 29 ++++++++++++++++++------ > > drivers/net/qede/qede_ethdev.h | 47 ++++++++++++++++++++++++--- > ------------ > > 3 files changed, 57 insertions(+), 26 deletions(-) > > > > diff --git a/drivers/net/qede/base/ecore_dev.c > > b/drivers/net/qede/base/ecore_dev.c > > index 5a29c45b..03620d94 100644 > > --- a/drivers/net/qede/base/ecore_dev.c > > +++ b/drivers/net/qede/base/ecore_dev.c > > @@ -2365,7 +2365,12 @@ static enum _ecore_status_t > > ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, #endif > > > > for (res_id =3D 0; res_id < ECORE_MAX_RESC; res_id++) { > > - rc =3D ecore_hw_set_resc_info(p_hwfn, res_id, > drv_resc_alloc); > > + /* @@@TMP for AH: > > + * Force the driver's default resource allocation in case there > > + * is a diff with the MFW allocation value. > > + */ > > + rc =3D ecore_hw_set_resc_info(p_hwfn, res_id, > > + b_ah || drv_resc_alloc); >=20 > Just to double check, is above code piece is related to the "add PCI ids = for > new chip variant" ? Yes, that is correct. In case of new chip variant AH, we force the driver's= default resource allocation if it differs from management firmware allocat= ion value. =20 > > if (rc !=3D ECORE_SUCCESS) > > return rc; > > } > <...>