From: "Van Haaren, Harry" <harry.van.haaren@intel.com>
To: "Honnappa Nagarahalli" <Honnappa.Nagarahalli@arm.com>,
"Morten Brørup" <mb@smartsharesystems.com>,
"Mattias Rönnblom" <hofors@lysator.liu.se>,
"mattias.ronnblom" <mattias.ronnblom@ericsson.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: nd <nd@arm.com>, nd <nd@arm.com>
Subject: RE: Service core statistics MT safety
Date: Fri, 8 Jul 2022 12:58:09 +0000 [thread overview]
Message-ID: <BN0PR11MB57121F50C7A0805E884000E6D7829@BN0PR11MB5712.namprd11.prod.outlook.com> (raw)
In-Reply-To: <DBAPR08MB5814EE088AF1F59C8AE1E5B198839@DBAPR08MB5814.eurprd08.prod.outlook.com>
> -----Original Message-----
> From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Sent: Thursday, July 7, 2022 6:26 PM
> To: Van Haaren, Harry <harry.van.haaren@intel.com>; Morten Brørup
> <mb@smartsharesystems.com>; Mattias Rönnblom <hofors@lysator.liu.se>;
> mattias.ronnblom <mattias.ronnblom@ericsson.com>; dev@dpdk.org
> Cc: nd <nd@arm.com>; nd <nd@arm.com>
> Subject: RE: Service core statistics MT safety
>
> <snip>
<snip>
> > Yes, understood and agree. Per-core counters are preferred, as relaxed atomic
> > ordered stores are enough to ensure non-tearing loads. Summation before
> > reporting back from the stats-requesting thread.
> > For backporting, per-core counters is a significant change. Is using atomics to fix
> > the miss-behaviour a better idea?
> Agree, the change will be simple.
>
> This will result in some perf impact which can be mitigated by disabling the stats
> where possible.
Yes, agree, disabling stats is a workaround if they're not required yep.
Correctness > performance. We can optimize to per-CPU stats in a future release.
> > My question below is still open, is the below enough to fix the *functional* part
> > of MT services?
> >
> > Code today uses normal ADD/INCQ (and hence the MT increments bug of
> > tear/clobber exists)
> > 0x000055555649189d <+141>: add %rax,0x50(%rbx)
> > 0x00005555564918a1 <+145>: incq 0x48(%rbx)
> >
> > For x86, my disassembly for RELAXED and SEQ_CST orderings are the same,
> > using LOCK prefix ("proper atomics")
> > 0x000055555649189d <+141>: lock add %rax,0x50(%rbx)
> > 0x00005555564918a2 <+146>: lock incq 0x48(%rbx)
> >
> > My understanding is that since 2x threads can write the same address, SEQ_CST
> > is required.
> > Can somebody more familiar with C11 confirm that?
> We need to use RELAXED. You can think of it as, 'do we need a particular order for
> memory operations within a single thread?' In this case, we do not need a particular
> order for incrementing stats in the single thread context.
Thanks for confirming; makes sense.
2 patches sent, you're on CC.
prev parent reply other threads:[~2022-07-08 12:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 11:05 Mattias Rönnblom
2022-06-27 12:31 ` Morten Brørup
2022-06-27 17:39 ` Honnappa Nagarahalli
2022-06-27 17:47 ` Mattias Rönnblom
2022-06-27 18:19 ` Honnappa Nagarahalli
2022-06-27 20:00 ` Mattias Rönnblom
2022-06-28 0:14 ` Honnappa Nagarahalli
2022-06-28 6:52 ` Mattias Rönnblom
2022-06-28 15:24 ` Honnappa Nagarahalli
2022-06-28 18:30 ` Mattias Rönnblom
2022-06-28 19:15 ` Honnappa Nagarahalli
2022-06-29 6:34 ` Mattias Rönnblom
2022-06-29 20:07 ` Honnappa Nagarahalli
2022-06-30 8:46 ` Van Haaren, Harry
2022-07-01 18:37 ` Honnappa Nagarahalli
2022-07-01 20:51 ` Morten Brørup
2022-07-05 17:09 ` Van Haaren, Harry
2022-07-07 17:26 ` Honnappa Nagarahalli
2022-07-08 12:58 ` Van Haaren, Harry [this message]
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