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Mon, 7 Sep 2020 08:34:45 +0000 From: "Wu, Jingjing" To: "Li, Xiaoyun" CC: "dev@dpdk.org" , "Maslekar, Omkar" Thread-Topic: [PATCH v3] raw/ntb: add Icelake support for Intel NTB Thread-Index: AQHWhL2fpnvJBLYfoEe/O5Gnb3HmMKlc1A1w Date: Mon, 7 Sep 2020 08:34:45 +0000 Message-ID: References: <20200831045958.5589-1-xiaoyun.li@intel.com> <20200907022112.17640-1-xiaoyun.li@intel.com> In-Reply-To: <20200907022112.17640-1-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.102.204.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 765d33ca-a804-4e67-fd60-08d85308dfe4 x-ms-traffictypediagnostic: BN6PR11MB3906: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN6PR11MB4052.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 765d33ca-a804-4e67-fd60-08d85308dfe4 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2020 08:34:45.2895 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1P9jp/DcRXyT7dthX1FtYvuQD9CWyMxpHs1FYn7k7gd53vu6mJ278TubmXZtmq/GFpRdDmfJedb6/0eLCbxDVQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB3906 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3] raw/ntb: add Icelake support for Intel NTB X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > + > +static int > +intel_ntb_dev_init(const struct rte_rawdev *dev) { > + struct ntb_hw *hw =3D dev->dev_private; > + uint8_t bar; > + int ret, i; > + > + if (hw =3D=3D NULL) { > + NTB_LOG(ERR, "Invalid device."); > + return -EINVAL; > + } > + > hw->hw_addr =3D (char *)hw->pci_dev->mem_resource[0].addr; >=20 > + if (is_gen3_ntb(hw)) { > + ret =3D intel_ntb3_check_ppd(hw); > + } else if (is_gen4_ntb(hw)) { > + /* PPD is in MMIO but not config space for NTB Gen4 */ > + ret =3D intel_ntb4_check_ppd(hw); > + if (ret) > + return ret; Above two lines are not necessary. > + } else { > + return -ENOTSUP; > + } > + > + if (ret) > + return ret; > + > hw->mw_cnt =3D XEON_MW_COUNT; > hw->db_cnt =3D XEON_DB_COUNT; > hw->spad_cnt =3D XEON_SPAD_COUNT; > @@ -149,15 +219,28 @@ intel_ntb_mw_set_trans(const struct rte_rawdev > *dev, int mw_idx, > rte_write64(base, xlat_addr); > rte_write64(limit, limit_addr); >=20 > - /* Setup the external point so that remote can access. */ > - xlat_off =3D XEON_EMBAR1_OFFSET + 8 * mw_idx; > - xlat_addr =3D hw->hw_addr + xlat_off; > - limit_off =3D XEON_EMBAR1XLMT_OFFSET + mw_idx * > XEON_BAR_INTERVAL_OFFSET; > - limit_addr =3D hw->hw_addr + limit_off; > - base =3D rte_read64(xlat_addr); > - base &=3D ~0xf; > - limit =3D base + size; > - rte_write64(limit, limit_addr); > + if (is_gen3_ntb(hw)) { > + /* Setup the external point so that remote can access. */ > + xlat_off =3D XEON_EMBAR1_OFFSET + 8 * mw_idx; > + xlat_addr =3D hw->hw_addr + xlat_off; > + limit_off =3D XEON_EMBAR1XLMT_OFFSET + > + mw_idx * XEON_BAR_INTERVAL_OFFSET; > + limit_addr =3D hw->hw_addr + limit_off; > + base =3D rte_read64(xlat_addr); > + base &=3D ~0xf; > + limit =3D base + size; > + rte_write64(limit, limit_addr); > + } else if (is_gen4_ntb(hw)) { Can we use a variable in struct to indicate it's gen4 or gen3 after init in= stead of check it every time? > + /* Set translate base address index register */ > + xlat_off =3D XEON_GEN4_IM1XBASEIDX_OFFSET + > + mw_idx * XEON_GEN4_XBASEIDX_INTERVAL; > + xlat_addr =3D hw->hw_addr + xlat_off; > + rte_write16(rte_log2_u64(size), xlat_addr); > + } else { > + rte_write64(base, limit_addr); > + rte_write64(0, xlat_addr); > + return -ENOTSUP; > + } Is the else branch necessary? As if neither gen3 or gen4, the init would fa= il. Would be better to print an ERR instead of just return NO support. >=20 > return 0; > }