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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 81e1c818-8c95-4bbd-84c2-08da47881ce9 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jun 2022 06:45:15.2380 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EvH41vM/eAPw5GG+7Ac6+S6vrlYPfHGk8rTTqKcHMtobw5PUPW8UovWo3MuhZMUUU/ZVAxJXH7Nl94uY/1uKxA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4464 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Huang, Wei <wei.huang@intel.com> > Sent: Friday, May 27, 2022 4:34 PM > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com; > hemant.agrawal@nxp.com > Cc: stable@dpdk.org; Xu, Rosen <rosen.xu@intel.com>; Zhang, Tianfei > <tianfei.zhang@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Huang, Wei > <wei.huang@intel.com> > Subject: [PATCH v4 5/5] guides/rawdevs: add description of ofs in ifpga d= oc >=20 > OFS (Open FPGA Stack) specification is introduced briefly. >=20 > Signed-off-by: Wei Huang <wei.huang@intel.com> > Reviewed-by: Rosen Xu <rosen.xu@intel.com> > --- > v2: update description per Tianfei's comment > --- > doc/guides/rawdevs/ifpga.rst | 105 > ++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 104 insertions(+), 1 deletion(-) >=20 > diff --git a/doc/guides/rawdevs/ifpga.rst b/doc/guides/rawdevs/ifpga.rst = index > dbd0d6e..3dce57a 100644 > --- a/doc/guides/rawdevs/ifpga.rst > +++ b/doc/guides/rawdevs/ifpga.rst > @@ -1,5 +1,5 @@ > .. SPDX-License-Identifier: BSD-3-Clause > - Copyright(c) 2018 Intel Corporation. > + Copyright(c) 2018-2022 Intel Corporation. >=20 > IFPGA Rawdev Driver > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > @@ -100,3 +100,106 @@ The following device parameters are supported: >=20 > If null, the AFU Bit Stream has been PR in FPGA, if not forces PR and > identifies AFU Bit Stream file. > + > + > +Open FPGA Stack > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > +Open FPGA Stack (OFS) is a collection of RTL and open source software > +providing interfaces to access the instantiated RTL easily in an FPGA. > +OFS leverages the DFL for the implementation of the FPGA RTL design. > + > +OFS designs allow for the arrangement of software interfaces across > +multiple PCIe endpoints. Some of these interfaces may be PFs defined in > +the static region that connect to interfaces in an IP that is loaded via= Partial > Reconfiguration (PR). > +And some of these interfaces may be VFs defined in the PR region that > +can be reconfigured by the end-user. Furthermore, these PFs/VFs may use > +DFLs such that features may be discovered and accessed in user space > +with the aid of a generic kernel driver like vfio-pci. The diagram > +below depicts an example design with one PF and two VFs. In this > +example, it will export the management functions via PF0 and > +acceleration functions via VF0 and VF1, leverage VFIO to export the MMIO > space to an application.:: > + > + +-----------------+ +-------------+ +------------+ > + | FPGA Management | | DPDK App | | User App | > + | App | | | | | > + +--------+--------+ +------+------+ +-----+------+ > + | | | > + +--------+--------+ +------+------+ | > + |IFPGA PMD driver | |AFU MF driver| | > + +--------+--------+ +------+------+ | > + | | | > + +--------+------------------+---------------+------+ > + | VFIO-PCI | > + +--------+------------------+---------------+------+ > + | | | > + +--------+--------+ +------+------+ +----+------+ > + | PF0 | | PF0_VF0 | | PF0_VF1 | > + +-----------------+ +-------------+ +-----------+ > + > +As accelerators are specialized hardware, they are typically limited in > +the number installed in a given system. Many use cases require them to > +be shared across multiple software contexts or threads of software > +execution, either through partitioning of individual dedicated > +resources, or virtualization of shared resources. OFS provides several > +models to share the AFU resources via PR mechanism and hardware-based > virtualization schemes. > + > +1. Legacy model. > + With legacy model FPGA cards like Intel PAC N3000 or N5000, there is > + a notion that the boundary between the AFU and the shell is also the = unit of > + PR for those FPGA platforms. This model is only able to handle a > + single context, because it only has one PR engine, and one PR region = which > + has an associated Port device. > +2. Multiple VFs per PR slot. > + In this model, available AFU resources may allow instantiation of man= y VFs > + which have a dedicated PCIe function with their own dedicated MMIO sp= ace, > or > + partition a region of MMIO space on a single PCIe function. Intel PAC= N6000 > + card has implemented this model. > + In this model, the AFU/PR slot was not connected to port device. For = DFL's > view, > + the Next_AFU pointer in FIU feature header of port device points to N= ULL in > this > + model. On the other hand, each VF can start with an AFU feature heade= r > without > + being connected to a FIU Port feature header. > + > +The VFs are created through the Linux kernel driver before we use them i= n > DPDK. > + > +OFS provides the diversity for accessing the AFU resource to RTL develop= er. > +An IP designer may choose to add more than one PF for interfacing with > +IP on the FPGA and choose different model to access the AFU resource. > + > +There is one reference architecture design using the "Multiple VFs per P= R slot" > +model for OFS as illustrated below. In this reference design, it > +exports the FPGA management functions via PF0. PF1 will bind with DPDK > +virtio driver presenting itself as a network interface to the > +application. PF2 will bind to the vfio-pci driver allowing the user > +space software to discover and interface with the specific workload > +like diagnostic test. It leverages AFU PMD driver to access the AFU reso= urces in > DPDK.:: > + > + +----------------------+ > + | PF/VF mux/demux | > + +--+--+-----+------+-+-+ > + | | | | | > + +------------------------+ | | | | > + PF0 | +---------+ +-+ | | > + +---+---+ | +---+----+ | | > + | DFH | | | DFH | | | > + +-------+ +-----+----+ +--------+ | | > + | FME | | VirtIO | | Test | | | > + +---+---+ +----------+ +--------+ | | > + | PF1 PF2 | | > + | | | > + | +----------+ | > + | | ++ > + | | | > + | | PF0_VF0 | PF0_VF1 > + | +-----------------+-----------+------------+ > + | | +-----+-----------+--------+ | > + | | | | | | | > + | | +------+ | +--+ -+ +--+---+ | | > + | | | Port | | | DFH | | DFH | | | > + +-----------+ +------+ | +-----+ +------+ | | > + | | | DEV | | DEV | | | > + | | +-----+ +------+ | | > + | | PR Slot | | > + | +--------------------------+ | > + | Port Gasket | > + +------------------------------------------+ > -- It looks good for me, you can add: Acked-by: Tianfei Zhang <tianfei.zhang@intel.com>