From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D05BAA0093; Fri, 17 Jun 2022 10:57:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BD832410D2; Fri, 17 Jun 2022 10:57:58 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 07ACB40698; Fri, 17 Jun 2022 10:57:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655456277; x=1686992277; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=f9bof63UE2cHXectryyLdrkcbTxLCglmvIV/OkSNQ8Y=; b=JxTS2JvyQ6zx/GtQWH8DIzgSD+MBK0mPixSEtYpeJC7tH6bBYbWbRtq3 yKjK/FwWZCVLk0p8kK+esiX0XzOXoRFJQWjSexrIaPNnWOEPS23ekEU0R KsQA4rmeu/VG/2BQ4W5rjU9VbpAlFFqxNuNFSWkgNuRlM7yY8CUWt124K LJ7kLvDfqn23W5iElh6TI+QvUIuPFk3l71Jh2F+JmWmjJuVJgUXrPPwe9 nSvSyED7maFcW8axEyPzKE7vWslRkoSQFbnXYqOsAC6Ijd2e7lGWXTBeA w7U1eUjibHYXLjI7Wn1DAmD9bwW212IV1r9edA1ryTjFFVq/y0C3ISU+h g==; X-IronPort-AV: E=McAfee;i="6400,9594,10380"; a="280489681" X-IronPort-AV: E=Sophos;i="5.92,306,1650956400"; d="scan'208";a="280489681" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2022 01:57:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,306,1650956400"; d="scan'208";a="912535093" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by fmsmga005.fm.intel.com with ESMTP; 17 Jun 2022 01:57:55 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Fri, 17 Jun 2022 01:57:55 -0700 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Fri, 17 Jun 2022 01:57:54 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Fri, 17 Jun 2022 01:57:54 -0700 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.108) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Fri, 17 Jun 2022 01:57:54 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D06YJJlDgQWxnBrDUlqQd/PXDim6FXC13KDsWtwwMMi9qPQoEc6gHlKl0+G2XwhJ3ahFc7eKAlOU2rgs90LsI/IyLoFl1dcCBKgmqBzxgey4CqdTVoL8qNwlhSJAXzNyQAns2tjOpyKLJL0cWO1xrnSB7wDusHHLAzwzrDkj/A8onrnaNSwV9ML21292MYF/M6TMWL0XjP2H/70c7+26deGB+b6tAP0DrLGBmLHL5vv3tlI26eBhpZQ4IWDvocHJh/44cJU85lvt80YwdjcQwewX7CAQDBkS/g4uNePqzxNZsmOoZpwQOiyyw3Mi7/9ammbm+pI6EJJeJzcgR2eFMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Odtbz1XMA5WQGqkatio/7utxocxA7rLfPTfsC5tty78=; b=F7y/H4EGL26jWf1dhQI9PzLfpheW0SxD+xkRQkTKRAcwA8WV3iztCl3ErZHZJ2F+LYjzaDMz4bLRkSIiDgpReQeP0swD84fmKFLE8d1/dm1Bb0pLvdAsWXnVOe5jGAX5jA/45hzIANvzIdOSUEVwNUtnKFdWAEYV3BDvnpdduaG5KuXiTtHbtNKlnvNKccHxpQyil7PZxNGY2nSbtTjMlx7XDOLj8LD7typANTuvp/xXdfmq4upz7E2sC8fIWDZL1C7evhHyqR6lD7N6aVaAKFws1N0vJmGBUPNeTHvb3KTj67cZatizaRcYU/NpbvCioOWrxkHpVFDjFgftzqKRKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from BN9PR11MB5483.namprd11.prod.outlook.com (2603:10b6:408:104::10) by DM4PR11MB6237.namprd11.prod.outlook.com (2603:10b6:8:a9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5332.19; Fri, 17 Jun 2022 08:57:52 +0000 Received: from BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::a113:c892:d94:dd10]) by BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::a113:c892:d94:dd10%7]) with mapi id 15.20.5353.015; Fri, 17 Jun 2022 08:57:52 +0000 From: "Zhang, Tianfei" To: "Huang, Wei" , "dev@dpdk.org" , "thomas@monjalon.net" , "nipun.gupta@nxp.com" , "hemant.agrawal@nxp.com" CC: "stable@dpdk.org" , "Xu, Rosen" , "Zhang, Qi Z" Subject: RE: [PATCH v3 2/4] raw/ifpga/base: update board information Thread-Topic: [PATCH v3 2/4] raw/ifpga/base: update board information Thread-Index: AQHYghmG0dcHiEl8z0qn+P9BUOZcZK1TTGYA Date: Fri, 17 Jun 2022 08:57:52 +0000 Message-ID: References: <1654827900-10023-1-git-send-email-wei.huang@intel.com> <1655450375-10739-1-git-send-email-wei.huang@intel.com> <1655450375-10739-3-git-send-email-wei.huang@intel.com> In-Reply-To: <1655450375-10739-3-git-send-email-wei.huang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.500.17 dlp-reaction: no-action authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ce51d5fc-64da-40ac-550a-08da503f7645 x-ms-traffictypediagnostic: DM4PR11MB6237:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: hHbBqiQdWZCGbadStGciA5c6+6Al6MH/jdWvLjPJ8OTxSpAQoL1oa0prBLA2T+EuApoN+HG0kNaxggNhgDskFOfUth72cmBInWABDvOPCCwgZfbQtNRAxVZe9lwlx9oT3ciKFeO0qYzCWGbALu9jhz1qTxfP/50hqEEDCtKPJBzt2xi+BbIN6Y51Tc3bIahfiLwiJnHAOGg9aZqcpVLvs/VBsZ579gybzBrABlZ4usgyMxBPM1lT2sFHKmDRc4PQKt+1nZ+dazGTd3F2YcAXEFPOcHPPxgij605XQTZ3Ik6aM4WHNM2yZAmqS98fSakSnANNqYQUbQxHfyxFeuzZmAYZpOU5JxrJvA9bSMyJGO8Ku7ripf5DdxxJRONxrOtnzNvGgZlx8ZblvWGKxvcc72HxZfho59rBPl7xzWaVQcn4AzNIMKd0B9f8fL9Kwegn1RtDLGBCL5xsx6z9SKezRpveLbg2XeHkRb9vZX14d52r5B/C6RbrEugSvHbURcq6mwzVZyivcsAd4UrPEVHvUwiVKYzt+JOaQsYJbTHBqvAm5/k+xWzpQZZK9Q4UsCLdYjOZa+5Q0jdEy9gAhAPeWrHneLulf+BZGdJ1JpIsT4X9cCWpDRtBAcyqbq5kZORcFku5nzJzzxGJc+dLVQSyOTbbq23YLZ6VQCjOUvKlZG20w013ikIh0akh2wEq3vy/IqSzVHbdlwzp8S/yNef4Hw== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN9PR11MB5483.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(366004)(53546011)(2906002)(64756008)(186003)(76116006)(9686003)(122000001)(66476007)(15650500001)(66556008)(82960400001)(38100700002)(110136005)(6506007)(66946007)(8676002)(55016003)(7696005)(83380400001)(316002)(5660300002)(66446008)(8936002)(52536014)(30864003)(71200400001)(4326008)(38070700005)(107886003)(86362001)(33656002)(54906003)(498600001); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 2 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?ANus793Sn0IF6MhLHRufJPu6UDaKNQrxXrL6PtVzCohLmkITl+QHzrKQHlLE?= =?us-ascii?Q?7IMARFZdRByr4y8qf2bl38Uz3LYi1w+f+d46Y9zm4NvJRQp5QKvMSbpkJNRV?= =?us-ascii?Q?WIoRar11sx5A+4D35LxLwlfSa2JZNQ5ySC07Y1qa3WYEa37T9OScF/R3qRUK?= =?us-ascii?Q?Hgb2KrIAZab4F0651j1LsyEfiF5ZabUvfd2LyS2pjxepMTBJVwPOcmA7QPPv?= =?us-ascii?Q?YaZEEdguIDJxqrRg8MSu183TnxsdLTT4ap/rnVQT8HSshNLLurDK6npxvLSu?= =?us-ascii?Q?jmurTZGEclDcWtN7KPGVncfLyWJZDXL9VHKTkzs+wroNp9OMFbKsxbht5sk3?= =?us-ascii?Q?mbs1mLwlS7HseiSl0OyZoWEcoUmH/goHRVSgVnc5QgwC4cMlLLFTjh6w1xEo?= =?us-ascii?Q?uZ/Vrm8rTa5qaITxKdp47njMfp7RUtSJfvorEAo8UWafHxIqORm/+5R6V4v6?= =?us-ascii?Q?ho0IfDykeJJ2IuNqdWKxq2yQBnJm0t+jcTVGrpjyr4uR/tkTeLPlujieVbbA?= =?us-ascii?Q?uedy0fnGTYQd+P0VnKTVtuwsx1w3CyFud+2ZxOACKVidRKnagYOdpGoU1OS0?= =?us-ascii?Q?MKEw01DHaLFRyKFIY65mn2IbFmsirTxf8Bqez5W+40SZYHZ2Ac/mKoZQp/8T?= =?us-ascii?Q?+h0Gil6Qkkc1zkXZWkci/2fACOVSMTGnd1Vc7+tlup+7nNkkkX96Gqv9NO2c?= =?us-ascii?Q?nEa5w3iuh3t1dFvphabS/2IVKdoV2HJ1TAKmp1Q/vVU5GHPAjhu0iDHGSs4t?= =?us-ascii?Q?NkB+eH6JHa1BJOcpSL0dea0fzlCGZl6LJamLY0vkOtmnEWl02qwaDXuUX+gG?= =?us-ascii?Q?n/uezIPN/ZGoCXtBfRWSf92fkklrvExEy2Hz7yF3K46vwf2cyB9OPHEDhNcH?= =?us-ascii?Q?FIADeuzQdRcsHZZ56EEZK5SQXll43dJ6G5UJ0KRPq0XSnPM63jY+oXED87IT?= =?us-ascii?Q?qqVHkx16GWfT3K3vsLBFn2aBTiX6H8A2g05Ok8HdlEcbzZMkQ2UJ6+kz6/8I?= =?us-ascii?Q?bwvYMVHKBWtaERQGkgZpa8ggEekJ6DNxuSoLQNbOGbcGmH0pH/6BxpIiD17h?= =?us-ascii?Q?gunb5TQqo2F1mtKXjsBYFyKDk4RNtQWEbxbptZRrueb7rqgRwtK2TkUD+8KU?= =?us-ascii?Q?vQc1Oi+eRD9PIkY86hF4nMQ4wPT0QaEFXWG8NaedtMPKhDPYLSZkan2Mnj8Q?= =?us-ascii?Q?sidKU+dh0nkwahsHxz70M6YbpQ4tUatneZv4/MaJ4ZPEOMnuf7ic0JwRrjt1?= =?us-ascii?Q?tCBNRwPH0yaDSHh8p92RdaUYakiowHspefIxa0hcY6OnYa6n/TD8xr4HiWO/?= =?us-ascii?Q?0qtq7xwn/iE7JJnG3h7n1DPseM6HpGZoUNIGMuSqqvTVghWVVoOV1Nw4IhOs?= =?us-ascii?Q?tBlZGaD8GHTyOwQ7rHrYlJchhU+FITXe3OQwugPk1XXz+Y92viZukdUFG5gB?= =?us-ascii?Q?gT+GzZfFoWJ8qjK0X4R2yB8ThY+fS6LxwsGRK6VkLpgzK09snNr0k5Awyc3U?= =?us-ascii?Q?0lLAXYiP2dyts41avhiG6zfIvH0v2xIwWm7IsqAO4Vl3zieZqG7m+ZMOZA7X?= =?us-ascii?Q?TWG7wbPUgkgWV/T4DaHDq9mqClTdJhpQZ9xtXSzJbP8aW1aNvcTrhmVkrxj3?= =?us-ascii?Q?KooAtDu1089qYVMaDfas8VUCEzS7sdqVfYuAnbbs9+CXZZjLP+QWUTmCgPP3?= =?us-ascii?Q?+KaFwjeKyHoj9MFvZdJkemHvz6xJlq5DunINzARat9A75yi0AmLJC3ytx/kp?= =?us-ascii?Q?kEg57y9UVVq9B5PQp1WpocateHJOnjb1feTAbC3ahvMoykUIJ0U9EvdVJksi?= x-ms-exchange-antispam-messagedata-1: EdKJXZ2CCRHhUK0bnos6CuPjb8Fay4WruwI= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ce51d5fc-64da-40ac-550a-08da503f7645 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2022 08:57:52.3450 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yK1aNqU8od18EImJynud+YoFYFGPKdd0R+Peh7P9tetqqww+LlQe8zBL13dvJcgBZ/cgqZY05VGmP054koCU+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6237 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Huang, Wei > Sent: Friday, June 17, 2022 3:20 PM > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com; > hemant.agrawal@nxp.com > Cc: stable@dpdk.org; Xu, Rosen ; Zhang, Tianfei > ; Zhang, Qi Z ; Huang, Wei > > Subject: [PATCH v3 2/4] raw/ifpga/base: update board information >=20 > N6000 ADP platform has different definition of board information, they ca= n be > recognized after this patch. >=20 > Signed-off-by: Wei Huang > --- > drivers/raw/ifpga/base/ifpga_defines.h | 101 +++++++++++++++---------= - > drivers/raw/ifpga/base/ifpga_fme.c | 121 ++++++++++++++++++++----= ------ > drivers/raw/ifpga/base/ifpga_fme_error.c | 2 + > drivers/raw/ifpga/base/ifpga_port_error.c | 2 +- > drivers/raw/ifpga/base/opae_intel_max10.c | 45 +++++++++++ > drivers/raw/ifpga/base/opae_intel_max10.h | 3 + > 6 files changed, 194 insertions(+), 80 deletions(-) >=20 > diff --git a/drivers/raw/ifpga/base/ifpga_defines.h > b/drivers/raw/ifpga/base/ifpga_defines.h > index f84ed1d..7c8fa89 100644 > --- a/drivers/raw/ifpga/base/ifpga_defines.h > +++ b/drivers/raw/ifpga/base/ifpga_defines.h > @@ -268,6 +268,24 @@ struct feature_fme_bitstream_id { > union { > u64 csr; > struct { > + u8 build_patch:8; > + u8 build_minor:8; > + u8 build_major:8; > + u8 fvl_bypass:1; > + u8 mac_lightweight:1; > + u8 disagregate:1; > + u8 lightweiht:1; > + u8 seu:1; > + u8 ptp:1; > + u8 reserve:2; > + u8 interface:4; > + u32 afu_revision:12; > + u8 patch:4; > + u8 minor:4; > + u8 major:4; > + u8 reserved:4; > + } v1; > + struct { > u32 gitrepo_hash:32; /* GIT repository hash */ > /* > * HSSI configuration identifier: > @@ -276,7 +294,8 @@ struct feature_fme_bitstream_id { > * 2 - Ethernet > */ > u8 hssi_id:4; > - u16 rsvd1:12; /* Reserved */ > + u8 rsvd1:4; > + u8 fim_type:8; > /* Bitstream version patch number */ > u8 bs_verpatch:4; > /* Bitstream version minor number */ @@ -285,7 > +304,7 @@ struct feature_fme_bitstream_id { > u8 bs_vermajor:4; > /* Bitstream version debug number */ > u8 bs_verdebug:4; > - }; > + } v2; > }; > }; >=20 > @@ -1672,31 +1691,6 @@ struct bts_header { >=20 > #define check_support(n) (n =3D=3D 1 ? "support" : "no") >=20 > -/* bitstream id definition */ > -struct fme_bitstream_id { > - union { > - u64 id; > - struct { > - u8 build_patch:8; > - u8 build_minor:8; > - u8 build_major:8; > - u8 fvl_bypass:1; > - u8 mac_lightweight:1; > - u8 disagregate:1; > - u8 lightweiht:1; > - u8 seu:1; > - u8 ptp:1; > - u8 reserve:2; > - u8 interface:4; > - u32 afu_revision:12; > - u8 patch:4; > - u8 minor:4; > - u8 major:4; > - u8 reserved:4; > - }; > - }; > -}; > - > enum board_interface { > VC_8_10G =3D 0, > VC_4_25G =3D 1, > @@ -1705,10 +1699,30 @@ enum board_interface { > VC_2_2_25G =3D 4, > }; >=20 > +enum fim_type { > + BASE_ADP =3D 0, > + BASE_FDK, > + BASE_X16_ADP, > + BASE_X16_FDK, > + FIMA_10G_ADP, > + FIMA_25G_ADP, > + FIMA_100G_ADP, > + FIMB_ADP, > + FIMC_ADP > +}; > + > +enum hssi_id { > + NO_HSSI =3D 0, > + PCIE_RP, > + ETHER_NET > +}; > + > enum pac_major { > VISTA_CREEK =3D 0, > RUSH_CREEK =3D 1, > DARBY_CREEK =3D 2, > + LIGHTNING_CREEK =3D 3, > + ARROW_CREEK =3D 5, > }; >=20 > enum pac_minor { > @@ -1720,23 +1734,30 @@ enum pac_minor { struct opae_board_info { > enum pac_major major; > enum pac_minor minor; > - enum board_interface type; > - > - /* PAC features */ > - u8 fvl_bypass; > - u8 mac_lightweight; > - u8 disaggregate; > - u8 lightweight; > - u8 seu; > - u8 ptp; >=20 > u32 boot_page; > u32 max10_version; > u32 nios_fw_version; > - u32 nums_of_retimer; > - u32 ports_per_retimer; > - u32 nums_of_fvl; > - u32 ports_per_fvl; > + > + union { > + struct { /* N3000 specific */ > + enum board_interface type; > + u8 fvl_bypass; > + u8 mac_lightweight; > + u8 disaggregate; > + u8 lightweight; > + u8 seu; > + u8 ptp; > + u32 nums_of_retimer; > + u32 ports_per_retimer; > + u32 nums_of_fvl; > + u32 ports_per_fvl; > + }; > + struct { > + enum fim_type n6000_fim_type; > + enum hssi_id n6000_hssi_id; > + }; > + }; > }; >=20 > #pragma pack(pop) > diff --git a/drivers/raw/ifpga/base/ifpga_fme.c > b/drivers/raw/ifpga/base/ifpga_fme.c > index 4d089d2..608a352 100644 > --- a/drivers/raw/ifpga/base/ifpga_fme.c > +++ b/drivers/raw/ifpga/base/ifpga_fme.c > @@ -790,19 +790,32 @@ struct ifpga_feature_ops fme_emif_ops =3D { > .uinit =3D fme_emif_uinit, > }; >=20 > -static const char *board_type_to_string(u32 type) -{ > - switch (type) { > - case VC_8_10G: > - return "VC_8x10G"; > - case VC_4_25G: > - return "VC_4x25G"; > - case VC_2_1_25: > - return "VC_2x1x25G"; > - case VC_4_25G_2_25G: > - return "VC_4x25G+2x25G"; > - case VC_2_2_25G: > - return "VC_2x2x25G"; > +static const char *board_type_to_string(u32 board, u32 type) { > + if (board =3D=3D VISTA_CREEK) { > + switch (type) { > + case VC_8_10G: > + return "8x10G"; > + case VC_4_25G: > + return "4x25G"; > + case VC_2_1_25: > + return "2x1x25G"; > + case VC_4_25G_2_25G: > + return "4x25G+2x25G"; > + case VC_2_2_25G: > + return "2x2x25G"; > + break; > + } > + } else { > + switch (type) { > + case FIMA_10G_ADP: > + return "2x4x10G"; > + case FIMA_25G_ADP: > + return "2x2x25G"; > + case FIMA_100G_ADP: > + return "2x100G"; > + break; > + } > } >=20 > return "unknown"; > @@ -817,6 +830,12 @@ static const char *board_major_to_string(u32 major) > return "RUSH_CREEK"; > case DARBY_CREEK: > return "DARBY_CREEK"; > + case LIGHTNING_CREEK: > + return "LIGHTNING_CREEK"; > + case ARROW_CREEK: > + return "ARROW_CREEK"; > + default: > + break; > } >=20 > return "unknown"; > @@ -859,35 +878,56 @@ static int board_type_to_info(u32 type, >=20 > static int fme_get_board_interface(struct ifpga_fme_hw *fme) { > - struct fme_bitstream_id id; > + struct feature_fme_bitstream_id id; > struct ifpga_hw *hw; > u32 val; > + const char *type =3D NULL; > + int ret; >=20 > hw =3D fme->parent; > if (!hw) > return -ENODEV; >=20 > - if (fme_hdr_get_bitstream_id(fme, &id.id)) > + if (fme_hdr_get_bitstream_id(fme, &id.csr)) > return -EINVAL; >=20 > - fme->board_info.major =3D id.major; > - fme->board_info.minor =3D id.minor; > - fme->board_info.type =3D id.interface; > - fme->board_info.fvl_bypass =3D id.fvl_bypass; > - fme->board_info.mac_lightweight =3D id.mac_lightweight; > - fme->board_info.lightweight =3D id.lightweiht; > - fme->board_info.disaggregate =3D id.disagregate; > - fme->board_info.seu =3D id.seu; > - fme->board_info.ptp =3D id.ptp; > + if (id.v1.major =3D=3D ARROW_CREEK) { > + fme->board_info.major =3D id.v2.bs_vermajor; > + fme->board_info.minor =3D id.v2.bs_verminor; > + fme->board_info.n6000_fim_type =3D id.v2.fim_type; > + fme->board_info.n6000_hssi_id =3D id.v2.hssi_id; > + type =3D board_type_to_string(fme->board_info.major, > + fme->board_info.n6000_fim_type); > + } else { > + fme->board_info.major =3D id.v1.major; > + fme->board_info.minor =3D id.v1.minor; > + fme->board_info.type =3D id.v1.interface; > + fme->board_info.fvl_bypass =3D id.v1.fvl_bypass; > + fme->board_info.mac_lightweight =3D id.v1.mac_lightweight; > + fme->board_info.lightweight =3D id.v1.lightweiht; > + fme->board_info.disaggregate =3D id.v1.disagregate; > + fme->board_info.seu =3D id.v1.seu; > + fme->board_info.ptp =3D id.v1.ptp; > + type =3D board_type_to_string(fme->board_info.major, > + fme->board_info.type); > + } >=20 > dev_info(fme, "found: PCI dev: %02x:%02x:%x board: %s type: %s\n", > hw->pci_data->bus, > hw->pci_data->devid, > hw->pci_data->function, > board_major_to_string(fme->board_info.major), > - board_type_to_string(fme->board_info.type)); > + type); >=20 > - dev_info(fme, "support feature:\n" > + ret =3D max10_get_fpga_load_info(fme->max10_dev, &val); > + if (ret) > + return ret; > + fme->board_info.boot_page =3D val; > + > + if (fme->board_info.major =3D=3D VISTA_CREEK) { > + dev_info(dev, "FPGA loaded from %s Image\n", > + val ? "User" : "Factory"); > + dev_info(fme, "support feature:\n" > "fvl_bypass:%s\n" > "mac_lightweight:%s\n" > "lightweight:%s\n" > @@ -901,26 +941,29 @@ static int fme_get_board_interface(struct > ifpga_fme_hw *fme) > check_support(fme->board_info.seu), > check_support(fme->board_info.ptp)); >=20 > + if (board_type_to_info(fme->board_info.type, &fme- > >board_info)) > + return -EINVAL; >=20 > - if (board_type_to_info(fme->board_info.type, &fme->board_info)) > - return -EINVAL; > - > - dev_info(fme, "get board info: nums_retimers %d ports_per_retimer %d > nums_fvl %d ports_per_fvl %d\n", > + dev_info(fme, "get board info: nums_retimers %d " > + "ports_per_retimer %d nums_fvl %d " > + "ports_per_fvl %d\n", > fme->board_info.nums_of_retimer, > fme->board_info.ports_per_retimer, > fme->board_info.nums_of_fvl, > fme->board_info.ports_per_fvl); > + } else { > + dev_info(dev, "FPGA loaded from %s Image\n", > + val ? (val =3D=3D 1 ? "User1" : "User2") : "Factory"); > + } >=20 > - if (max10_sys_read(fme->max10_dev, FPGA_PAGE_INFO, &val)) > - return -EINVAL; > - fme->board_info.boot_page =3D val & 0x7; > - > - if (max10_sys_read(fme->max10_dev, MAX10_BUILD_VER, &val)) > - return -EINVAL; > + ret =3D max10_get_bmc_version(fme->max10_dev, &val); > + if (ret) > + return ret; > fme->board_info.max10_version =3D val; >=20 > - if (max10_sys_read(fme->max10_dev, NIOS2_FW_VERSION, &val)) > - return -EINVAL; > + ret =3D max10_get_bmcfw_version(fme->max10_dev, &val); > + if (ret) > + return ret; > fme->board_info.nios_fw_version =3D val; >=20 > dev_info(fme, "max10 version 0x%x, nios fw version 0x%x\n", @@ - > 1023,7 +1066,7 @@ static int fme_spi_init(struct ifpga_feature *feature) > opae_free(max10); > release_dev: > altera_spi_release(spi_master); > - return ret; > + return -ENODEV; > } >=20 > static void fme_spi_uinit(struct ifpga_feature *feature) diff --git > a/drivers/raw/ifpga/base/ifpga_fme_error.c > b/drivers/raw/ifpga/base/ifpga_fme_error.c > index 5905eac..c5bed28 100644 > --- a/drivers/raw/ifpga/base/ifpga_fme_error.c > +++ b/drivers/raw/ifpga/base/ifpga_fme_error.c > @@ -224,6 +224,8 @@ static int fme_global_error_init(struct ifpga_feature > *feature) { > struct ifpga_fme_hw *fme =3D feature->parent; >=20 > + dev_info(NULL, "FME error_module Init.\n"); > + > fme_error_enable(fme); >=20 > if (feature->ctx_num) > diff --git a/drivers/raw/ifpga/base/ifpga_port_error.c > b/drivers/raw/ifpga/base/ifpga_port_error.c > index 189f762..6c8a7d7 100644 > --- a/drivers/raw/ifpga/base/ifpga_port_error.c > +++ b/drivers/raw/ifpga/base/ifpga_port_error.c > @@ -88,7 +88,7 @@ static int port_error_init(struct ifpga_feature *featur= e) { > struct ifpga_port_hw *port =3D feature->parent; >=20 > - dev_info(NULL, "port error Init.\n"); > + dev_info(NULL, "port error_module Init.\n"); >=20 > spinlock_lock(&port->lock); > port_err_mask(port, false); > diff --git a/drivers/raw/ifpga/base/opae_intel_max10.c > b/drivers/raw/ifpga/base/opae_intel_max10.c > index 901a258..26f323c 100644 > --- a/drivers/raw/ifpga/base/opae_intel_max10.c > +++ b/drivers/raw/ifpga/base/opae_intel_max10.c > @@ -766,6 +766,51 @@ static int max10_staging_area_init(struct > intel_max10_device *dev) > return 0; > } >=20 > +int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned > +int *val) { > + int ret; > + unsigned int value; > + > + /* read FPGA loading information */ > + ret =3D max10_sys_read(dev, dev->csr->fpga_page_info, &value); > + if (ret) { > + dev_err(dev, "fail to get FPGA loading info\n"); > + return ret; > + } > + > + if (dev->type =3D=3D M10_N3000) > + *val =3D value & 0x7; > + else if (dev->type =3D=3D M10_N6000) { > + if (!GET_FIELD(PMCI_FPGA_CONFIGURED, value)) > + return -EINVAL; > + *val =3D GET_FIELD(PMCI_FPGA_BOOT_PAGE, value); > + } > + > + return 0; > +} > + > +int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int > +*val) { > + int ret; > + > + ret =3D max10_sys_read(dev, dev->csr->build_version, val); > + if (ret) > + return ret; > + > + return 0; > +} > + > +int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned > +int *val) { > + int ret; > + > + ret =3D max10_sys_read(dev, dev->csr->fw_version, val); > + if (ret) > + return ret; > + > + return 0; > +} > + > static const struct m10bmc_csr m10bmc_spi_csr =3D { > .base =3D MAX10_SEC_BASE_ADDR, > .build_version =3D MAX10_BUILD_VER, > diff --git a/drivers/raw/ifpga/base/opae_intel_max10.h > b/drivers/raw/ifpga/base/opae_intel_max10.h > index 0d31196..6a1b122 100644 > --- a/drivers/raw/ifpga/base/opae_intel_max10.h > +++ b/drivers/raw/ifpga/base/opae_intel_max10.h > @@ -336,6 +336,9 @@ int max10_reg_write(struct intel_max10_device *dev, > unsigned int offset, unsigned int val); int max10_sys_update_bits(stru= ct > intel_max10_device *dev, > unsigned int offset, unsigned int msk, unsigned int val); > +int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned > +int *val); int max10_get_bmc_version(struct intel_max10_device *dev, > +unsigned int *val); int max10_get_fpga_load_info(struct > +intel_max10_device *dev, unsigned int *val); > int intel_max10_device_init(struct intel_max10_device *dev); int > intel_max10_device_remove(struct intel_max10_device *dev); >=20 > -- > 1.8.3.1 It looks good for me. Acked-by: Tianfei Zhang