> -----Original Message-----
> From: Shijith Thotton <sthotton@marvell.com>
> Sent: Thursday, September 25, 2025 5:39 PM
> To: Jerin Jacob <jerinj@marvell.com>
> Cc: Shijith Thotton <sthotton@marvell.com>; dev@dpdk.org; Pavan Nikhilesh
> Bhagavatula <pbhagavatula@marvell.com>
> Subject: [PATCH] event/cnxk: update queue weight mapping for CN20K
> 
> The CN20K platform accepts weights in the range of 1 to 255, while DPDK
> allows weights from 0 to 255. This patch aligns DPDK's weight values with the
> hardware-supported range.
> 
> Signed-off-by: Shijith Thotton <sthotton@marvell.com>


Applied to dpdk-next-net-eventdev/for-main. Thanks

> ---
>  drivers/event/cnxk/cn20k_eventdev.c | 70 ++++++++++++++++++++++++++++-
> drivers/event/cnxk/cn20k_eventdev.h |  1 +
>  2 files changed, 69 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/event/cnxk/cn20k_eventdev.c
> b/drivers/event/cnxk/cn20k_eventdev.c
> index 4552f6da97..b25e570211 100644
> --- a/drivers/event/cnxk/cn20k_eventdev.c
> +++ b/drivers/event/cnxk/cn20k_eventdev.c
> @@ -20,6 +20,72 @@
>  #define CN20K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops)
> \
>  	enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]
> 
> +static uint8_t
> +cn20k_sso_hw_weight(uint8_t weight)
> +{
> +	/* Map DPDK weight 0-255 to HW weight 1-255 */
> +	return (weight + 1) > CN20K_SSO_WEIGHT_MAX ?
> CN20K_SSO_WEIGHT_MAX :
> +(weight + 1); }
> +
> +static int
> +cn20k_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
> +		      const struct rte_event_queue_conf *queue_conf) {
> +	struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
> +	uint8_t priority, weight, affinity;
> +
> +	priority = CNXK_QOS_NORMALIZE(queue_conf->priority, 0,
> RTE_EVENT_DEV_PRIORITY_LOWEST,
> +				      CNXK_SSO_PRIORITY_CNT);
> +	weight = cn20k_sso_hw_weight(queue_conf->weight);
> +	affinity = CNXK_QOS_NORMALIZE(queue_conf->affinity, 0,
> RTE_EVENT_QUEUE_AFFINITY_HIGHEST,
> +				      CNXK_SSO_AFFINITY_CNT);
> +
> +	plt_sso_dbg("Queue=%u prio=%u weight=%u affinity=%u", queue_id,
> +priority, weight, affinity);
> +
> +	return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, weight,
> +affinity, priority); }
> +
> +static int
> +cn20k_sso_queue_attribute_set(struct rte_eventdev *event_dev, uint8_t
> queue_id, uint32_t attr_id,
> +			      uint64_t attr_value)
> +{
> +	struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
> +	uint8_t priority, weight, affinity;
> +	struct rte_event_queue_conf *conf;
> +
> +	conf = &event_dev->data->queues_cfg[queue_id];
> +
> +	switch (attr_id) {
> +	case RTE_EVENT_QUEUE_ATTR_PRIORITY:
> +		conf->priority = attr_value;
> +		break;
> +	case RTE_EVENT_QUEUE_ATTR_WEIGHT:
> +		conf->weight = attr_value;
> +		break;
> +	case RTE_EVENT_QUEUE_ATTR_AFFINITY:
> +		conf->affinity = attr_value;
> +		break;
> +	case RTE_EVENT_QUEUE_ATTR_NB_ATOMIC_FLOWS:
> +	case RTE_EVENT_QUEUE_ATTR_NB_ATOMIC_ORDER_SEQUENCES:
> +	case RTE_EVENT_QUEUE_ATTR_EVENT_QUEUE_CFG:
> +	case RTE_EVENT_QUEUE_ATTR_SCHEDULE_TYPE:
> +		/* FALLTHROUGH */
> +		plt_sso_dbg("Unsupported attribute id %u", attr_id);
> +		return -ENOTSUP;
> +	default:
> +		plt_err("Invalid attribute id %u", attr_id);
> +		return -EINVAL;
> +	}
> +
> +	priority = CNXK_QOS_NORMALIZE(conf->priority, 0,
> RTE_EVENT_DEV_PRIORITY_LOWEST,
> +				      CNXK_SSO_PRIORITY_CNT);
> +	weight = cn20k_sso_hw_weight(conf->weight);
> +	affinity = CNXK_QOS_NORMALIZE(conf->affinity, 0,
> RTE_EVENT_QUEUE_AFFINITY_HIGHEST,
> +				      CNXK_SSO_AFFINITY_CNT);
> +
> +	return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, weight,
> +affinity, priority); }
> +
>  static void *
>  cn20k_sso_init_hws_mem(void *arg, uint8_t port_id)  { @@ -1114,9 +1180,9
> @@ static struct eventdev_ops cn20k_sso_dev_ops = {
>  	.dev_configure = cn20k_sso_dev_configure,
> 
>  	.queue_def_conf = cnxk_sso_queue_def_conf,
> -	.queue_setup = cnxk_sso_queue_setup,
> +	.queue_setup = cn20k_sso_queue_setup,
>  	.queue_release = cnxk_sso_queue_release,
> -	.queue_attr_set = cnxk_sso_queue_attribute_set,
> +	.queue_attr_set = cn20k_sso_queue_attribute_set,
> 
>  	.port_def_conf = cnxk_sso_port_def_conf,
>  	.port_setup = cn20k_sso_port_setup,
> diff --git a/drivers/event/cnxk/cn20k_eventdev.h
> b/drivers/event/cnxk/cn20k_eventdev.h
> index 8ea2878fa5..71f1fc6086 100644
> --- a/drivers/event/cnxk/cn20k_eventdev.h
> +++ b/drivers/event/cnxk/cn20k_eventdev.h
> @@ -7,6 +7,7 @@
> 
>  #define CN20K_SSO_DEFAULT_STASH_OFFSET -1  #define
> CN20K_SSO_DEFAULT_STASH_LENGTH 2
> +#define CN20K_SSO_WEIGHT_MAX	       (0xff)
> 
>  struct __rte_cache_aligned cn20k_sso_hws {
>  	uint64_t base;
> --
> 2.25.1