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Tue, 15 Sep 2020 01:54:50 +0000 From: "Zhang, AlvinX" To: "Zhang, Qi Z" CC: "dev@dpdk.org" Thread-Topic: [PATCH v5] net/iavf: support outer IP hash for no inner GTPU Thread-Index: AQHWinZxGm22PjWH1U2iQvAQgc2HkKln7+sAgAEBZXA= Date: Tue, 15 Sep 2020 01:54:50 +0000 Message-ID: References: <20200910032623.38168-1-alvinx.zhang@intel.com> <20200914090316.49740-1-alvinx.zhang@intel.com> <66caca1e210445e38955d8cc5cdb3319@intel.com> In-Reply-To: <66caca1e210445e38955d8cc5cdb3319@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.102.204.45] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0cd3ab9b-cdb5-431f-dc7e-08d8591a554f x-ms-traffictypediagnostic: BYAPR11MB3559: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2803; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB3895.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0cd3ab9b-cdb5-431f-dc7e-08d8591a554f X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Sep 2020 01:54:50.6395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cdeDUAsIboIy10DnmC9yqd/Ke/gguJkrH03JL48FKmwUb7XkDtxXgJE9MpZKZMqAO/Ukm2EbZ0RYbIuiHYeNuQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3559 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5] net/iavf: support outer IP hash for no inner GTPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Thanks Zhangqi. > -----Original Message----- > From: Zhang, Qi Z > Sent: Monday, September 14, 2020 6:33 PM > To: Zhang, AlvinX ; Guo, Jia > Cc: dev@dpdk.org > Subject: RE: [PATCH v5] net/iavf: support outer IP hash for no inner GTPU >=20 >=20 >=20 > > -----Original Message----- > > From: Zhang, AlvinX > > Sent: Monday, September 14, 2020 5:03 PM > > To: Guo, Jia ; Zhang, Qi Z > > Cc: dev@dpdk.org; Zhang, AlvinX > > Subject: [PATCH v5] net/iavf: support outer IP hash for no inner GTPU > > > > From: Alvin Zhang > > > > Outer IP hash can be configured as input sets for no inner GTPU packets= . > > > > Signed-off-by: Alvin Zhang > > --- > > > > V2: Modify codes according to comments. > > V3: Refact all codes. > > V4: Fix compatibility issues. > > V5: Modify codes according to comments. > > > > drivers/net/iavf/iavf_hash.c | 48 > > ++++++++++++++++++++++++++------------------ > > 1 file changed, 28 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/net/iavf/iavf_hash.c > > b/drivers/net/iavf/iavf_hash.c index > > ff77d71..d0a6396 100644 > > --- a/drivers/net/iavf/iavf_hash.c > > +++ b/drivers/net/iavf/iavf_hash.c > > @@ -348,6 +348,7 @@ struct virtchnl_proto_hdrs ipv6_pfcp_tmplt =3D { > > {iavf_pattern_eth_vlan_ipv4_udp,IAVF_RSS_TYPE_VLAN_IPV4_UDP, > > &outer_ipv4_udp_tmplt}, > > {iavf_pattern_eth_vlan_ipv4_tcp,IAVF_RSS_TYPE_VLAN_IPV4_TCP, > > &outer_ipv4_tcp_tmplt}, > > {iavf_pattern_eth_vlan_ipv4_sctp,IAVF_RSS_TYPE_VLAN_IPV4_SCTP, > > &outer_ipv4_sctp_tmplt}, > > +{iavf_pattern_eth_ipv4_gtpu,ETH_RSS_IPV4, > > &outer_ipv4_udp_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv4,IAVF_RSS_TYPE_GTPU_IPV4, > > &inner_ipv4_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv4_udp, > > IAVF_RSS_TYPE_GTPU_IPV4_UDP,&inner_ipv4_udp_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv4_tcp, > > IAVF_RSS_TYPE_GTPU_IPV4_TCP,&inner_ipv4_tcp_tmplt}, > > @@ -374,6 +375,7 @@ struct virtchnl_proto_hdrs ipv6_pfcp_tmplt =3D { > > {iavf_pattern_eth_vlan_ipv6_udp,IAVF_RSS_TYPE_VLAN_IPV6_UDP, > > &outer_ipv6_udp_tmplt}, > > {iavf_pattern_eth_vlan_ipv6_tcp,IAVF_RSS_TYPE_VLAN_IPV6_TCP, > > &outer_ipv6_tcp_tmplt}, > > {iavf_pattern_eth_vlan_ipv6_sctp,IAVF_RSS_TYPE_VLAN_IPV6_SCTP, > > &outer_ipv6_sctp_tmplt}, > > +{iavf_pattern_eth_ipv6_gtpu,ETH_RSS_IPV6, > > &outer_ipv6_udp_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv6,IAVF_RSS_TYPE_GTPU_IPV6, > > &inner_ipv6_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv6_udp, > > IAVF_RSS_TYPE_GTPU_IPV6_UDP,&inner_ipv6_udp_tmplt}, > > {iavf_pattern_eth_ipv4_gtpu_ipv6_tcp, > > IAVF_RSS_TYPE_GTPU_IPV6_TCP,&inner_ipv6_tcp_tmplt}, > > @@ -698,31 +700,37 @@ struct virtchnl_proto_hdrs > > *iavf_hash_default_hdrs[] =3D { struct virtchnl_proto_hdr *hdr2; int > > i; > > > > -if (!(phint & IAVF_PHINT_GTPU_MSK) || > > - proto_hdrs->tunnel_level =3D=3D 0) > > +if (!(phint & IAVF_PHINT_GTPU_MSK)) > > return; > > > > -/* shift headers 1 layer */ > > -for (i =3D proto_hdrs->count; i > 0; i--) { > > -hdr1 =3D &proto_hdrs->proto_hdr[i]; > > -hdr2 =3D &proto_hdrs->proto_hdr[i - 1]; > > +if (proto_hdrs->tunnel_level =3D=3D TUNNEL_LEVEL_INNER) { > > +/* shift headers 1 layer */ > > +for (i =3D proto_hdrs->count; i > 0; i--) { > > +hdr1 =3D &proto_hdrs->proto_hdr[i]; > > +hdr2 =3D &proto_hdrs->proto_hdr[i - 1]; > > > > -*hdr1 =3D *hdr2; > > -} > > +*hdr1 =3D *hdr2; > > +} > > > > -/* adding gtpu header at layer 0 */ > > -proto_hdrs->count++; > > -hdr1 =3D &proto_hdrs->proto_hdr[0]; > > -hdr1->field_selector =3D 0; > > - > > -if (phint & IAVF_PHINT_GTPU_EH_DWN) > > -VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH_PDU_DWN); -else if > (phint & > > IAVF_PHINT_GTPU_EH_UP) -VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, > > GTPU_EH_PDU_UP); -else if (phint & IAVF_PHINT_GTPU_EH) > > -VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH); -else if (phint & > > IAVF_PHINT_GTPU) > > +/* adding gtpu header at layer 0 */ > > +proto_hdrs->count++; > > +hdr1 =3D &proto_hdrs->proto_hdr[0]; > > +hdr1->field_selector =3D 0; > > + > > +if (phint & IAVF_PHINT_GTPU_EH_DWN) > > +VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH_PDU_DWN); else if > (phint & > > +IAVF_PHINT_GTPU_EH_UP) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, > > +GTPU_EH_PDU_UP); else if (phint & IAVF_PHINT_GTPU_EH) > > +VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH); else if (phint & > > +IAVF_PHINT_GTPU) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_IP); } > else { > > +hdr1 =3D &proto_hdrs->proto_hdr[proto_hdrs->count]; > > +hdr1->field_selector =3D 0; > > +proto_hdrs->count++; > > VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_IP); >=20 > Its better to also check phint for outer case, could be implemented as be= low >=20 > If (inner) { > Shift > Hdr =3D hdrs[0] > } > else { > Hdr =3D hdrs[count] > } >=20 > hdr-count++ >=20 > if (phint & IAVF_PHINT_GTPU_EH_DWN) > VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH_PDU_DWN); else if (phint & > IAVF_PHINT_GTPU_EH_UP) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, > GTPU_EH_PDU_UP); else if (phint & IAVF_PHINT_GTPU_EH) > VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_EH); else if (phint & > IAVF_PHINT_GTPU) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr1, GTPU_IP); >=20 >=20 > > +} > > } > > > > static void iavf_refine_proto_hdrs(struct virtchnl_proto_hdrs > > *proto_hdrs, > > -- > > 1.8.3.1 >=20