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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ce434935-4e11-4ed8-7b63-08dc33d0e07e X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Feb 2024 18:05:39.1877 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XVG8PstJ5TBNTb6mF4AlXkFzyfRCzx0ZGmHKraL/UuCjgik6GUAngzTeV3EgQDaQihGGKKzYebN/wtkyRuYsU0dyG4xiywdLiekcWqSAPUI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR11MB7178 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Maxime,=20 Why would we change this here and now? Is the intent not to use new suggest= ed semantics for new patches only? Are all DPDK drivers being changed? I am unsure we would want to change these drivers, this is kind of risk int= roduced by code churn that gets ecosystem unwilling to move to latest versi= on. These memory barriers issues are awful to troubleshoot or properly validate= , so personally quite reluctant to change.=20 Thanks Nic > -----Original Message----- > From: Maxime Coquelin > Sent: Thursday, February 22, 2024 8:21 AM > To: dev@dpdk.org; Chautru, Nicolas ; Vargas, > Hernan ; Marchand, David > ; thomas@monjalon.net; > roretzla@linux.microsoft.com > Cc: Maxime Coquelin > Subject: [PATCH 1/2] baseband/fpga_5gnr_fec: use new barrier API >=20 > rte_smp_rmb() is deprecated, use the new API instead as suggested in > rte_atomic header. >=20 > Signed-off-by: Maxime Coquelin > --- > drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index efc1d3a772..314c87350e 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -2661,7 +2661,7 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct > fpga_5gnr_queue *q, struct rte_bbdev_e > return -1; >=20 > /* make sure the response is read atomically */ > - rte_smp_rmb(); > + rte_atomic_thread_fence(rte_memory_order_acquire); >=20 > rte_bbdev_log_debug("DMA response desc %p", desc); >=20 > @@ -2690,7 +2690,7 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct > fpga_5gnr_queue *q, struct rte_bbdev_en > return -1; >=20 > /* make sure the response is read atomically. */ > - rte_smp_rmb(); > + rte_atomic_thread_fence(rte_memory_order_acquire); >=20 > rte_bbdev_log_debug("DMA response desc %p", desc); >=20 > @@ -2722,7 +2722,7 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct > fpga_5gnr_queue *q, struct rte_bbdev_d > return -1; >=20 > /* make sure the response is read atomically */ > - rte_smp_rmb(); > + rte_atomic_thread_fence(rte_memory_order_acquire); >=20 > #ifdef RTE_LIBRTE_BBDEV_DEBUG > vc_5gnr_print_dma_dec_desc_debug_info(desc); > @@ -2768,7 +2768,7 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct > fpga_5gnr_queue *q, struct rte_bbdev_de > return -1; >=20 > /* make sure the response is read atomically. */ > - rte_smp_rmb(); > + rte_atomic_thread_fence(rte_memory_order_acquire); >=20 > #ifdef RTE_LIBRTE_BBDEV_DEBUG > agx100_print_dma_dec_desc_debug_info(desc); > -- > 2.43.0