From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 292EDA034F; Tue, 5 Oct 2021 01:23:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A0A94410F0; Tue, 5 Oct 2021 01:23:43 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 113CE4068F for ; Tue, 5 Oct 2021 01:23:40 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10127"; a="225552401" X-IronPort-AV: E=Sophos;i="5.85,347,1624345200"; d="scan'208";a="225552401" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2021 16:23:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,347,1624345200"; d="scan'208";a="559020652" Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by FMSMGA003.fm.intel.com with ESMTP; 04 Oct 2021 16:23:38 -0700 Received: from orsmsx603.amr.corp.intel.com (10.22.229.16) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Mon, 4 Oct 2021 16:23:38 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12 via Frontend Transport; Mon, 4 Oct 2021 16:23:38 -0700 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.174) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2242.12; Mon, 4 Oct 2021 16:23:38 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HG+GOnzr8yd3BIakHCASINBPN62KPxpIIHQWJdxNljogs458FEux26Qh7d4HkibvhH5fudqCv4MJdlljN+Y2Nan/0VXKwhSTmP97krPz+78wyTDPJTXyTz8roaTCOsYwu9tGhpdJVE5cvQKl9zjyVzSilfm362T8EC3HTO500CU9pLW1W3T1eZrtCsQt70nHFLsi1ww+hWYFCBwBQWe5FC1GxawLFS6519JkwPAhj8e9t/f9K0CaZ/wt9msi+5cEq7jRdlYIRxZYUWT3JcAKeoinukiGLcddMQq2qU2m2ica2zffwRPB3PJvjMAGgCE2+cJEmQe82QNkXZzSC88HeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QnhgkBLf07zprXwe+Xc6QWJQGFWUu/6lgRAzHCNh+qU=; b=lhOVvwsJ3bdVa6WzhIe8Vsjz7ey3Nwu5GgNwCbEJ9y+YKqPYjpp5/aYafv+dz6ZKSzVf119nZ+ftSAflC9JmnwwpRNFAkV84eiO5nx8vSZ1z6SUbXcvi4UL/c+gyta7INpBAxInu5MmXSjS+VLv6kCHhkYnLQzJPx3l9QMi387JCSAXv+raaYLePeIzeMMWiJX8SX1dsbwQCYiwPjnGcgXlmAQMT0iru2pp/lLZhzWGTw/47MrVB3arRS+D71Z9uxKtfHXjzfdEqHEXOKK0OHHtKHWuGIlUXVlQkfCO8hei55ZS2QgnS/XdHKkiMirnBOaChpTk8xbxSE+6X4CrouQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QnhgkBLf07zprXwe+Xc6QWJQGFWUu/6lgRAzHCNh+qU=; b=zxBwsLzRS/UBoKe0kXHaci71To7eir8ljmplVfxCjlFU/+rjCTTTFSUODXQJGqwGQoiASkhf1Lu7dNaG4UXC832Jc9/zn+d+u8zlC9vY/4frZtl2CB7SWJTupIW91VgyIxQQeJ+BuGe/4GiFz9tmHtoc1n37iao6vg0lsu03ras= Received: from BY5PR11MB4451.namprd11.prod.outlook.com (2603:10b6:a03:1cb::30) by SJ0PR11MB4831.namprd11.prod.outlook.com (2603:10b6:a03:2d2::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14; Mon, 4 Oct 2021 23:23:37 +0000 Received: from BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::d2d:4882:88be:85bd]) by BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::d2d:4882:88be:85bd%7]) with mapi id 15.20.4566.022; Mon, 4 Oct 2021 23:23:37 +0000 From: "Chautru, Nicolas" To: "nipun.gupta@nxp.com" , "dev@dpdk.org" , "gakhil@marvell.com" CC: "david.marchand@redhat.com" , "hemant.agrawal@nxp.com" Thread-Topic: [PATCH v7 6/9] baseband/la12xx: add enqueue and dequeue support Thread-Index: AQHXtEMNQDNJa2iIzU2BFElcVUtVMavDhJAg Date: Mon, 4 Oct 2021 23:23:37 +0000 Message-ID: References: <20210318063421.14895-1-hemant.agrawal@nxp.com> <20210928082953.18731-1-nipun.gupta@nxp.com> <20210928082953.18731-7-nipun.gupta@nxp.com> In-Reply-To: <20210928082953.18731-7-nipun.gupta@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bb30b57d-364d-4da8-e412-08d9878dfe2c x-ms-traffictypediagnostic: SJ0PR11MB4831: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:383; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ripJKQWinAs9FYHoS3T3al4U9z9rhw1JCCCr3mWth+tBPzJP5wmB3jSvybQWGfK2xYns6RIv+3NkT4c9rRYxeHGaaTLCVhLvqGB7qOGotw5mwAXzXd70AfsMoZP8v/0XSOkoaJJzL/6loyf6Y1RVGYBbafwaTylYxUcHl2wmSgqTFBBve5xwU+k4zcFlHL6X5NfLyVcJlVn3LWBbMa9dS7PzrDYHeJnMDLtuLNuIxpLYPNOeveROmc2TM+v7gZiWUu9n/i1ZXYk/5Bz2xKMFb4rhzWX7SRu6ovvhMqVODBKSQdIyvM7eqQlaS6NZwp9OuQfasEXqX7YyQPkOa/2yckSr18mP2eFjaMLpXPQMOj2Rt7VGPhtYpjlvHz1xoVpZb8JTf9AS3bb9xMtpMdAxBijnGmxfs6zUHAEGTvPAGdsqrnXfUnkq6LwlhZpLKpl07DSjJMwyPASIaYPw+luBLIKASYCbK5KpGDJ5rryw6S6bM9YQkkSLc9Lz5ScBJu7oJ/6V08HYZT3ZN3AlTefLN29g+nMCGS87IRd1+9Op8hI82ht43dapquaG3b9ueZ7yKN9sSPD7XYexwIZJrJgnGfLXoBMK5n3hFaqKFdp1NyfRT6kIWuFKeEDYAFTqiRHDu1wzk8p3bkYxh/bdS1SaeD6cGqRzvlgStbKwUS+mUtdobKQ9etPl6Rl9eJlV5XgL+WrvDCYBOF2ttLLZ64uC4A== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BY5PR11MB4451.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(316002)(4326008)(30864003)(38100700002)(83380400001)(8936002)(38070700005)(2906002)(110136005)(86362001)(122000001)(66556008)(66476007)(76116006)(64756008)(6506007)(54906003)(66946007)(5660300002)(66446008)(33656002)(8676002)(55016002)(53546011)(71200400001)(7696005)(186003)(52536014)(9686003)(508600001)(26005)(579004); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?K4Tan9TywB+Vr8Pqat28lj+2ztig6EffmcTES8kmnDW7LtoWOiJlFkzaChb9?= =?us-ascii?Q?AfKTPEhg5vnRUHVBJo0t9pC2szLWjAD94rYR0ZFJclqcqOpSl8W3Z9MuIobM?= =?us-ascii?Q?lFhfjCb+XrqzwHqVHKCFZKOq3mYrTAcp0UWAvAagoUKXu1MfsD6IVDqcgUQx?= =?us-ascii?Q?X+lBIAFOqiL052s4ylzJEZyPTfJXBjRMfFtHBWudB0q/X+MDdVxx5EUTRItX?= =?us-ascii?Q?cLkcUOW04R4JQoKBnifDL0LFTp/G+lqp6mlp+J/Jj5HSbYS0csg0VvTOUIy9?= =?us-ascii?Q?eSj5N2tK9BmhIsmoLYyJcBHOYQma3HU3rFa/H1em15Zg2bsqcawPEwBCasHd?= =?us-ascii?Q?QWMHs4b8Cp8FaSBnSwcf1IYLgcD+aEaSrO+zxrVaj1U5uCGRYbz9x5oh/UZD?= =?us-ascii?Q?k841JHagHCZubMUxJPw+CDt01jHkKO5UHSt/wTIVXzZxXR2nCTDTJAVqozVW?= =?us-ascii?Q?FEbzXRaAVUGmNTjT8ZaoUs9dDSdsuVw7prjjC+rZe+VpSZYtNf5Ut4nR4ndo?= =?us-ascii?Q?K1ButQlG9h6PyU62qGePH7tZRFaTEqjjUFoeJn9v8sOM1A93a/6Ap1z99lMk?= =?us-ascii?Q?q/pHhIUFH2K/ElMww9bRoqItWIbXWTqaYG7UwpG+z4+0ZLqKBUcwn9/XqSvN?= =?us-ascii?Q?iVrfOtczBNye79/Y8zM4wk07fIzIL/ABtuEhbKgqGarF5p9RGgwNvmMU72Um?= =?us-ascii?Q?DLwYnuqAI6cRJ3ckp95IKLHWmPdoRyfq9Gq0FYZFtepKjqGvOJgxQJnd4pKd?= =?us-ascii?Q?s7bKhuomIJ3AgkObQFkhJssqYOfyfXF4GUtNGB9dJRiqEx7nOVxQpYXnVs5I?= =?us-ascii?Q?bI/TJqWdUqk6+WdGxblxddXsflyVPCbJoi631EEY1X7rLuLxgG/4ufoKxbRj?= =?us-ascii?Q?TTW8OsBYwtPmu1tYl2vjM1KdRyT27YaxE/yGo2MxhJV+W9Pj04HUPfZuvzI2?= =?us-ascii?Q?sj1dX/p0VEhvyUUwPV5W9wBlSPJtBsT9nQiSoyQ1bcwOZSInIg5IrBLH1BUO?= =?us-ascii?Q?BWCTO4xeRK0MAed+9InvHNX4w09/a0ZjfW0TpqkeRvTt40L+8kHVd6neSy6j?= =?us-ascii?Q?L5V9Ru7zbgQvRXUv3/BdxOeTuBeqhO9rcFmG0Hdreg6IEYM6ye3HfQI8cnKG?= =?us-ascii?Q?SqM/TDs5rkDZ0L6qyj9vevNTc0ZSWIfSVI1l5Go2UdDgcQtmz+vh8p2bYxcZ?= =?us-ascii?Q?7gp4itjIDgKlgJowbZy6HFQ1XF55mm0Y5CyOuOEOpiq7IEGaLZ80Rpv+8DUt?= =?us-ascii?Q?SMdvyAWVUrd6Anm5M1gd+lyor1vdC66Mzsj/KnSrLe9pmcHz54XHaDW6uJmh?= =?us-ascii?Q?c6WViwfJmTNZUG4gEIUu7tWn?= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb30b57d-364d-4da8-e412-08d9878dfe2c X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Oct 2021 23:23:37.2610 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KloFLZnDPsrVUU0YBHNbKYQ5qnEJIJT7il17rRHINduujlhuxxaZwYjY/YQVBR5dqeCA/IFA4D6pIVTNjnUYgIfJH7VNGStAUe8A4014OdU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB4831 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v7 6/9] baseband/la12xx: add enqueue and dequeue support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: nipun.gupta@nxp.com > Sent: Tuesday, September 28, 2021 1:30 AM > To: dev@dpdk.org; gakhil@marvell.com; Chautru, Nicolas > > Cc: david.marchand@redhat.com; hemant.agrawal@nxp.com; Nipun Gupta > > Subject: [PATCH v7 6/9] baseband/la12xx: add enqueue and dequeue > support >=20 > From: Hemant Agrawal >=20 > Add support for enqueue and dequeue the LDPC enc/dec from the modem > device. >=20 > Signed-off-by: Nipun Gupta > Signed-off-by: Hemant Agrawal > --- > doc/guides/bbdevs/features/la12xx.ini | 13 + > doc/guides/bbdevs/la12xx.rst | 47 ++- > drivers/baseband/la12xx/bbdev_la12xx.c | 328 ++++++++++++++++++++- > drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 37 +++ > 4 files changed, 420 insertions(+), 5 deletions(-) create mode 100644 > doc/guides/bbdevs/features/la12xx.ini >=20 > diff --git a/doc/guides/bbdevs/features/la12xx.ini > b/doc/guides/bbdevs/features/la12xx.ini > new file mode 100644 > index 0000000000..0aec5eecb6 > --- /dev/null > +++ b/doc/guides/bbdevs/features/la12xx.ini > @@ -0,0 +1,13 @@ > +; > +; Supported features of the 'la12xx' bbdev driver. > +; > +; Refer to default.ini for the full list of available PMD features. > +; > +[Features] > +Turbo Decoder (4G) =3D N > +Turbo Encoder (4G) =3D N > +LDPC Decoder (5G) =3D Y > +LDPC Encoder (5G) =3D Y > +LLR/HARQ Compression =3D N > +HW Accelerated =3D Y > +BBDEV API =3D Y > diff --git a/doc/guides/bbdevs/la12xx.rst b/doc/guides/bbdevs/la12xx.rst > index 3c9ac5c047..b111ec0dd6 100644 > --- a/doc/guides/bbdevs/la12xx.rst > +++ b/doc/guides/bbdevs/la12xx.rst > @@ -16,10 +16,11 @@ Features >=20 > LA12xx PMD supports the following features: >=20 > +- LDPC Encode in the DL > +- LDPC Decode in the UL > - Maximum of 8 UL queues > - Maximum of 8 DL queues > - PCIe Gen-3 x8 Interface > -- MSI-X >=20 > Installation > ------------ > @@ -79,3 +80,47 @@ For enabling logs, use the following EAL parameter: >=20 > Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can = be > enabled which are lower than logging ``level``. > + > +Test Application > +---------------- > + > +BBDEV provides a test application, ``test-bbdev.py`` and range of test > +data for testing the functionality of LA12xx for FEC encode and decode, > +depending on the device capabilities. The test application is located > +under app->test-bbdev folder and has the following options: > + > +.. code-block:: console > + > + "-p", "--testapp-path": specifies path to the bbdev test app. > + "-e", "--eal-params" : EAL arguments which are passed to the test app. > + "-t", "--timeout" : Timeout in seconds (default=3D300). > + "-c", "--test-cases" : Defines test cases to run. Run all if not speci= fied. > + "-v", "--test-vector" : Test vector path (default=3Ddpdk_path+/app/tes= t- > bbdev/test_vectors/bbdev_null.data). > + "-n", "--num-ops" : Number of operations to process on device > (default=3D32). > + "-b", "--burst-size" : Operations enqueue/dequeue burst size > (default=3D32). > + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests. > + "-s", "--iter_max" : Number of iterations for LDPC decoder. > + "-l", "--num-lcores" : Number of lcores to run (default=3D16). > + "-i", "--init-device" : Initialise PF device with default values. > + > + > +To execute the test application tool using simple decode or encode > +data, type one of the following: > + > +.. code-block:: console > + > + ./test-bbdev.py > + -e=3D"--vdev=3Dbaseband_la12xx,socket_id=3D0,max_nb_queues=3D8" -c vali= dation > + -n 64 -b 1 -v ./ldpc_dec_default.data ./test-bbdev.py > + -e=3D"--vdev=3Dbaseband_la12xx,socket_id=3D0,max_nb_queues=3D8" -c vali= dation > + -n 64 -b 1 -v ./ldpc_enc_default.data > + > +The test application ``test-bbdev.py``, supports the ability to > +configure the PF device with a default set of values, if the "-i" or "- > +-init-device" option is included. The default values are defined in > test_bbdev_perf.c. > + > + > +Test Vectors > +~~~~~~~~~~~~ > + > +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev > +also provides a range of additional tests under the test_vectors > +folder, which may be useful. The results of these tests will depend on > +the LA12xx FEC capabilities which may cause some testcases to be skipped= , > but no failure should be reported. > diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c > b/drivers/baseband/la12xx/bbdev_la12xx.c > index 46ee5b4d70..69ca83cee6 100644 > --- a/drivers/baseband/la12xx/bbdev_la12xx.c > +++ b/drivers/baseband/la12xx/bbdev_la12xx.c > @@ -120,6 +120,10 @@ la12xx_queue_release(struct rte_bbdev *dev, > uint16_t q_id) > ((uint64_t) ((unsigned long) (A) \ > - ((uint64_t)ipc_priv->hugepg_start.host_vaddr))) >=20 > +#define MODEM_P2V(A) \ > + ((uint64_t) ((unsigned long) (A) \ > + + (unsigned long)(ipc_priv->peb_start.host_vaddr))) > + > static int ipc_queue_configure(uint32_t channel_id, > ipc_t instance, struct bbdev_la12xx_q_priv *q_priv) { @@ - > 334,6 +338,318 @@ static const struct rte_bbdev_ops pmd_ops =3D { > .queue_release =3D la12xx_queue_release, > .start =3D la12xx_start > }; > + > +static inline int > +is_bd_ring_full(uint32_t ci, uint32_t ci_flag, > + uint32_t pi, uint32_t pi_flag) > +{ > + if (pi =3D=3D ci) { > + if (pi_flag !=3D ci_flag) > + return 1; /* Ring is Full */ > + } > + return 0; > +} > + > +static inline int > +prepare_ldpc_enc_op(struct rte_bbdev_enc_op *bbdev_enc_op, > + struct bbdev_la12xx_q_priv *q_priv __rte_unused, > + struct rte_bbdev_op_data *in_op_data __rte_unused, > + struct rte_bbdev_op_data *out_op_data) { > + struct rte_bbdev_op_ldpc_enc *ldpc_enc =3D &bbdev_enc_op- > >ldpc_enc; > + uint32_t total_out_bits; > + > + total_out_bits =3D (ldpc_enc->tb_params.cab * > + ldpc_enc->tb_params.ea) + (ldpc_enc->tb_params.c - > + ldpc_enc->tb_params.cab) * ldpc_enc->tb_params.eb; > + > + ldpc_enc->output.length =3D (total_out_bits + 7)/8; > + > + rte_pktmbuf_append(out_op_data->data, ldpc_enc->output.length); > + > + return 0; > +} > + > +static inline int > +prepare_ldpc_dec_op(struct rte_bbdev_dec_op *bbdev_dec_op, > + struct bbdev_ipc_dequeue_op *bbdev_ipc_op, > + struct bbdev_la12xx_q_priv *q_priv __rte_unused, > + struct rte_bbdev_op_data *out_op_data __rte_unused) { > + struct rte_bbdev_op_ldpc_dec *ldpc_dec =3D &bbdev_dec_op- > >ldpc_dec; > + uint32_t total_out_bits; > + uint32_t num_code_blocks =3D 0; > + uint16_t sys_cols; > + > + sys_cols =3D (ldpc_dec->basegraph =3D=3D 1) ? 22 : 10; > + if (ldpc_dec->tb_params.c =3D=3D 1) { > + total_out_bits =3D ((sys_cols * ldpc_dec->z_c) - > + ldpc_dec->n_filler); > + /* 5G-NR protocol uses 16 bit CRC when output packet > + * size <=3D 3824 (bits). Otherwise 24 bit CRC is used. > + * Adjust the output bits accordingly > + */ > + if (total_out_bits - 16 <=3D 3824) > + total_out_bits -=3D 16; > + else > + total_out_bits -=3D 24; > + ldpc_dec->hard_output.length =3D (total_out_bits / 8); > + } else { > + total_out_bits =3D (((sys_cols * ldpc_dec->z_c) - > + ldpc_dec->n_filler - 24) * > + ldpc_dec->tb_params.c); > + ldpc_dec->hard_output.length =3D (total_out_bits / 8) - 3; > + } > + > + num_code_blocks =3D ldpc_dec->tb_params.c; > + > + bbdev_ipc_op->num_code_blocks =3D > rte_cpu_to_be_32(num_code_blocks); > + > + return 0; > +} > + > +static int > +enqueue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *bbdev_op) { > + struct bbdev_la12xx_private *priv =3D q_priv->bbdev_priv; > + ipc_userspace_t *ipc_priv =3D priv->ipc_priv; > + ipc_instance_t *ipc_instance =3D ipc_priv->instance; > + struct bbdev_ipc_dequeue_op *bbdev_ipc_op; > + struct rte_bbdev_op_ldpc_enc *ldpc_enc; > + struct rte_bbdev_op_ldpc_dec *ldpc_dec; > + uint32_t q_id =3D q_priv->q_id; > + uint32_t ci, ci_flag, pi, pi_flag; > + ipc_ch_t *ch =3D &(ipc_instance->ch_list[q_id]); > + ipc_br_md_t *md =3D &(ch->md); > + size_t virt; > + char *huge_start_addr =3D > + (char *)q_priv->bbdev_priv->ipc_priv- > >hugepg_start.host_vaddr; > + struct rte_bbdev_op_data *in_op_data, *out_op_data; > + char *data_ptr; > + uint32_t l1_pcie_addr; > + int ret; > + > + ci =3D IPC_GET_CI_INDEX(q_priv->host_ci); > + ci_flag =3D IPC_GET_CI_FLAG(q_priv->host_ci); > + > + pi =3D IPC_GET_PI_INDEX(q_priv->host_pi); > + pi_flag =3D IPC_GET_PI_FLAG(q_priv->host_pi); > + > + rte_bbdev_dp_log(DEBUG, "before bd_ring_full: pi: %u, ci: %u," > + "pi_flag: %u, ci_flag: %u, ring size: %u", > + pi, ci, pi_flag, ci_flag, q_priv->queue_size); > + > + if (is_bd_ring_full(ci, ci_flag, pi, pi_flag)) { > + rte_bbdev_dp_log(DEBUG, "bd ring full for queue id: %d", > q_id); > + return IPC_CH_FULL; > + } > + > + virt =3D MODEM_P2V(q_priv->host_params->bd_m_modem_ptr[pi]); > + bbdev_ipc_op =3D (struct bbdev_ipc_dequeue_op *)virt; > + q_priv->bbdev_op[pi] =3D bbdev_op; > + > + switch (q_priv->op_type) { > + case RTE_BBDEV_OP_LDPC_ENC: > + ldpc_enc =3D &(((struct rte_bbdev_enc_op *)bbdev_op)- > >ldpc_enc); > + in_op_data =3D &ldpc_enc->input; > + out_op_data =3D &ldpc_enc->output; > + > + ret =3D prepare_ldpc_enc_op(bbdev_op, q_priv, > + in_op_data, out_op_data); > + if (ret) { > + rte_bbdev_log(ERR, "process_ldpc_enc_op fail, ret: > %d", > + ret); > + return ret; > + } > + break; > + > + case RTE_BBDEV_OP_LDPC_DEC: > + ldpc_dec =3D &(((struct rte_bbdev_dec_op *)bbdev_op)- > >ldpc_dec); > + in_op_data =3D &ldpc_dec->input; > + > + out_op_data =3D &ldpc_dec->hard_output; > + > + ret =3D prepare_ldpc_dec_op(bbdev_op, bbdev_ipc_op, > + q_priv, out_op_data); > + if (ret) { > + rte_bbdev_log(ERR, "process_ldpc_dec_op fail, ret: > %d", > + ret); > + return ret; > + } > + break; > + > + default: > + rte_bbdev_log(ERR, "unsupported bbdev_ipc op type"); > + return -1; > + } > + > + if (in_op_data->data) { > + data_ptr =3D rte_pktmbuf_mtod(in_op_data->data, char *); > + l1_pcie_addr =3D (uint32_t)GUL_USER_HUGE_PAGE_ADDR + > + data_ptr - huge_start_addr; > + bbdev_ipc_op->in_addr =3D l1_pcie_addr; > + bbdev_ipc_op->in_len =3D in_op_data->length; > + } > + > + if (out_op_data->data) { > + data_ptr =3D rte_pktmbuf_mtod(out_op_data->data, char *); > + l1_pcie_addr =3D (uint32_t)GUL_USER_HUGE_PAGE_ADDR + > + data_ptr - huge_start_addr; > + bbdev_ipc_op->out_addr =3D > rte_cpu_to_be_32(l1_pcie_addr); > + bbdev_ipc_op->out_len =3D rte_cpu_to_be_32(out_op_data- > >length); > + } > + > + /* Move Producer Index forward */ > + pi++; > + /* Flip the PI flag, if wrapping */ > + if (unlikely(q_priv->queue_size =3D=3D pi)) { > + pi =3D 0; > + pi_flag =3D pi_flag ? 0 : 1; > + } > + > + if (pi_flag) > + IPC_SET_PI_FLAG(pi); > + else > + IPC_RESET_PI_FLAG(pi); > + q_priv->host_pi =3D pi; > + > + /* Wait for Data Copy & pi_flag update to complete before updating > pi */ > + rte_mb(); > + /* now update pi */ > + md->pi =3D rte_cpu_to_be_32(pi); > + > + rte_bbdev_dp_log(DEBUG, "enter: pi: %u, ci: %u," > + "pi_flag: %u, ci_flag: %u, ring size: %u", > + pi, ci, pi_flag, ci_flag, q_priv->queue_size); > + > + return 0; > +} > + > +/* Enqueue decode burst */ > +static uint16_t > +enqueue_dec_ops(struct rte_bbdev_queue_data *q_data, > + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) { > + struct bbdev_la12xx_q_priv *q_priv =3D q_data->queue_private; > + int nb_enqueued, ret; > + > + for (nb_enqueued =3D 0; nb_enqueued < nb_ops; nb_enqueued++) { > + ret =3D enqueue_single_op(q_priv, ops[nb_enqueued]); > + if (ret) > + break; > + } > + > + q_data->queue_stats.enqueue_err_count +=3D nb_ops - > nb_enqueued; > + q_data->queue_stats.enqueued_count +=3D nb_enqueued; > + > + return nb_enqueued; > +} > + > +/* Enqueue encode burst */ > +static uint16_t > +enqueue_enc_ops(struct rte_bbdev_queue_data *q_data, > + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) { > + struct bbdev_la12xx_q_priv *q_priv =3D q_data->queue_private; > + int nb_enqueued, ret; > + > + for (nb_enqueued =3D 0; nb_enqueued < nb_ops; nb_enqueued++) { > + ret =3D enqueue_single_op(q_priv, ops[nb_enqueued]); > + if (ret) > + break; > + } > + > + q_data->queue_stats.enqueue_err_count +=3D nb_ops - > nb_enqueued; > + q_data->queue_stats.enqueued_count +=3D nb_enqueued; > + > + return nb_enqueued; > +} > + > +/* Dequeue encode burst */ > +static void * > +dequeue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *dst) { > + void *op; > + uint32_t ci, ci_flag; > + uint32_t temp_ci; > + > + temp_ci =3D q_priv->host_params->ci; > + if (temp_ci =3D=3D q_priv->host_ci) > + return NULL; > + > + ci =3D IPC_GET_CI_INDEX(q_priv->host_ci); > + ci_flag =3D IPC_GET_CI_FLAG(q_priv->host_ci); > + > + rte_bbdev_dp_log(DEBUG, > + "ci: %u, ci_flag: %u, ring size: %u", > + ci, ci_flag, q_priv->queue_size); > + > + op =3D q_priv->bbdev_op[ci]; > + > + rte_memcpy(dst, q_priv->msg_ch_vaddr[ci], > + sizeof(struct bbdev_ipc_enqueue_op)); > + > + /* Move Consumer Index forward */ > + ci++; > + /* Flip the CI flag, if wrapping */ > + if (q_priv->queue_size =3D=3D ci) { > + ci =3D 0; > + ci_flag =3D ci_flag ? 0 : 1; > + } > + if (ci_flag) > + IPC_SET_CI_FLAG(ci); > + else > + IPC_RESET_CI_FLAG(ci); > + > + q_priv->host_ci =3D ci; > + > + rte_bbdev_dp_log(DEBUG, > + "exit: ci: %u, ci_flag: %u, ring size: %u", > + ci, ci_flag, q_priv->queue_size); > + > + return op; > +} > + > +/* Dequeue decode burst */ > +static uint16_t > +dequeue_dec_ops(struct rte_bbdev_queue_data *q_data, > + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) { > + struct bbdev_la12xx_q_priv *q_priv =3D q_data->queue_private; > + struct bbdev_ipc_enqueue_op bbdev_ipc_op; > + int nb_dequeued; > + > + for (nb_dequeued =3D 0; nb_dequeued < nb_ops; nb_dequeued++) { > + ops[nb_dequeued] =3D dequeue_single_op(q_priv, > &bbdev_ipc_op); > + if (!ops[nb_dequeued]) > + break; > + ops[nb_dequeued]->status =3D bbdev_ipc_op.status; > + } > + q_data->queue_stats.dequeued_count +=3D nb_dequeued; > + > + return nb_dequeued; > +} > + > +/* Dequeue encode burst */ > +static uint16_t > +dequeue_enc_ops(struct rte_bbdev_queue_data *q_data, > + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) { > + struct bbdev_la12xx_q_priv *q_priv =3D q_data->queue_private; > + struct bbdev_ipc_enqueue_op bbdev_ipc_op; > + int nb_enqueued; > + > + for (nb_enqueued =3D 0; nb_enqueued < nb_ops; nb_enqueued++) { > + ops[nb_enqueued] =3D dequeue_single_op(q_priv, > &bbdev_ipc_op); > + if (!ops[nb_enqueued]) > + break; > + ops[nb_enqueued]->status =3D bbdev_ipc_op.status; > + } > + q_data->queue_stats.enqueued_count +=3D nb_enqueued; > + > + return nb_enqueued; > +} > + > static struct hugepage_info * > get_hugepage_info(void) > { > @@ -710,10 +1026,14 @@ la12xx_bbdev_create(struct rte_vdev_device > *vdev, > bbdev->intr_handle =3D NULL; >=20 > /* register rx/tx burst functions for data path */ > - bbdev->dequeue_enc_ops =3D NULL; > - bbdev->dequeue_dec_ops =3D NULL; > - bbdev->enqueue_enc_ops =3D NULL; > - bbdev->enqueue_dec_ops =3D NULL; > + bbdev->dequeue_enc_ops =3D dequeue_enc_ops; > + bbdev->dequeue_dec_ops =3D dequeue_dec_ops; > + bbdev->enqueue_enc_ops =3D enqueue_enc_ops; > + bbdev->enqueue_dec_ops =3D enqueue_dec_ops; These functions are for 4G which are not supported here. These can be kept = as NULL. The ones used for LDPC are below.=20 > + bbdev->dequeue_ldpc_enc_ops =3D dequeue_enc_ops; > + bbdev->dequeue_ldpc_dec_ops =3D dequeue_dec_ops; > + bbdev->enqueue_ldpc_enc_ops =3D enqueue_enc_ops; > + bbdev->enqueue_ldpc_dec_ops =3D enqueue_dec_ops; >=20 > return 0; > } > diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h > b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h > index 5f613fb087..b6a7f677d0 100644 > --- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h > +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h > @@ -73,6 +73,25 @@ typedef struct { > _IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *) #define > IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int > *) >=20 > +#define GUL_USER_HUGE_PAGE_OFFSET (0) > +#define GUL_PCI1_ADDR_BASE (0x00000000ULL) > + > +#define GUL_USER_HUGE_PAGE_ADDR (GUL_PCI1_ADDR_BASE + > GUL_USER_HUGE_PAGE_OFFSET) > + > +/* IPC PI/CI index & flag manipulation helpers */ > +#define IPC_PI_CI_FLAG_MASK 0x80000000 /* (1<<31) */ > +#define IPC_PI_CI_INDEX_MASK 0x7FFFFFFF /* ~(1<<31) */ > + > +#define IPC_SET_PI_FLAG(x) (x |=3D IPC_PI_CI_FLAG_MASK) > +#define IPC_RESET_PI_FLAG(x) (x &=3D IPC_PI_CI_INDEX_MASK) > +#define IPC_GET_PI_FLAG(x) (x >> 31) > +#define IPC_GET_PI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) > + > +#define IPC_SET_CI_FLAG(x) (x |=3D IPC_PI_CI_FLAG_MASK) > +#define IPC_RESET_CI_FLAG(x) (x &=3D IPC_PI_CI_INDEX_MASK) > +#define IPC_GET_CI_FLAG(x) (x >> 31) > +#define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) > + > /** buffer ring common metadata */ > typedef struct ipc_bd_ring_md { > volatile uint32_t pi; /**< Producer index and flag (MSB) > @@ -180,6 +199,24 @@ struct bbdev_ipc_enqueue_op { > uint32_t rsvd; > }; >=20 > +/** Structure specifying dequeue operation (dequeue at LA1224) */ > +struct bbdev_ipc_dequeue_op { > + /** Input buffer memory address */ > + uint32_t in_addr; > + /** Input buffer memory length */ > + uint32_t in_len; > + /** Output buffer memory address */ > + uint32_t out_addr; > + /** Output buffer memory length */ > + uint32_t out_len; > + /* Number of code blocks. Only set when HARQ is used */ > + uint32_t num_code_blocks; > + /** Dequeue Operation flags */ > + uint32_t op_flags; > + /** Shared metadata between L1 and L2 */ > + uint32_t shared_metadata; > +}; > + > /* This shared memory would be on the host side which have copy of some > * of the parameters which are also part of Shared BD ring. Read access > * of these parameters from the host side would not be over PCI. > -- > 2.17.1