From: "Chautru, Nicolas" <nicolas.chautru@intel.com>
To: Thomas Monjalon <thomas@monjalon.net>,
"Mcnamara, John" <john.mcnamara@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
"Devlin, Michelle" <michelle.devlin@intel.com>
Subject: RE: Intel roadmap for 22.07
Date: Tue, 29 Mar 2022 15:13:41 +0000 [thread overview]
Message-ID: <BY5PR11MB44514DC22AE6108164C4FC7EF81E9@BY5PR11MB4451.namprd11.prod.outlook.com> (raw)
In-Reply-To: <3106786.vfdyTQepKt@thomas>
Hi Thomas,
The ACC101 PMD is to support a new silicon being PRQ this year by Intel. Note this is not a FPGA but an actual ASIC.
There is some similarity with ACC100 but still a brand new silicon, new features, number of silicon bug fixes, different number of engines, different performance and hence a separate PMD.
Let me know I unclear
Nic
> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Tuesday, March 29, 2022 5:15 AM
> To: Mcnamara, John <john.mcnamara@intel.com>
> Cc: dev@dpdk.org; Devlin, Michelle <michelle.devlin@intel.com>
> Subject: Re: Intel roadmap for 22.07
>
> 24/03/2022 09:32, Mcnamara, John:
> > * DLB allow assignment of SW/HW credit quanta assignment on port usage
> > hint
> > * DLB allow dlb2 eventdev apps to use specific COS on per port basis
> > * DLB add support for DLB 2.5 QE weight hardware feature
>
> DLB and DLB2 were introduced as different but very similar drivers, and they
> got eventually merged.
>
> > * bbdev new PMD for Intel ACC101 device
>
> Is it really going to be a separate driver of ACC100?
>
next prev parent reply other threads:[~2022-03-29 15:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 8:32 Mcnamara, John
2022-03-29 12:15 ` Thomas Monjalon
2022-03-29 15:13 ` Chautru, Nicolas [this message]
2022-03-29 18:51 ` Thomas Monjalon
2023-07-31 14:12 ` Thomas Monjalon
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