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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c1ff1c92-ee13-43f1-8fbf-08da1196b5e7 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Mar 2022 15:13:41.9714 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: s3/jUD5jt7dmCoUxku+UT1CDSA+MB0OHkzPCb8evZunaOk3SfjU2BI4v9w5i7XFBiVZaj2bAR+qzE1fPh7S8s82R/M/3b2kujs+4IYQuqGI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB4890 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Thomas,=20 The ACC101 PMD is to support a new silicon being PRQ this year by Intel. No= te this is not a FPGA but an actual ASIC.=20 There is some similarity with ACC100 but still a brand new silicon, new fea= tures, number of silicon bug fixes, different number of engines, different = performance and hence a separate PMD. Let me know I unclear Nic > -----Original Message----- > From: Thomas Monjalon > Sent: Tuesday, March 29, 2022 5:15 AM > To: Mcnamara, John > Cc: dev@dpdk.org; Devlin, Michelle > Subject: Re: Intel roadmap for 22.07 >=20 > 24/03/2022 09:32, Mcnamara, John: > > * DLB allow assignment of SW/HW credit quanta assignment on port usage > > hint > > * DLB allow dlb2 eventdev apps to use specific COS on per port basis > > * DLB add support for DLB 2.5 QE weight hardware feature >=20 > DLB and DLB2 were introduced as different but very similar drivers, and t= hey > got eventually merged. >=20 > > * bbdev new PMD for Intel ACC101 device >=20 > Is it really going to be a separate driver of ACC100? >=20