From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E382DA0C46; Fri, 17 Sep 2021 16:23:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 983B0410E9; Fri, 17 Sep 2021 16:23:41 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id C8235406B4 for ; Fri, 17 Sep 2021 16:23:39 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="283813661" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="283813661" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 07:23:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="472291391" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga007.fm.intel.com with ESMTP; 17 Sep 2021 07:23:38 -0700 Received: from fmsmsx606.amr.corp.intel.com (10.18.126.86) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 17 Sep 2021 07:23:38 -0700 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12 via Frontend Transport; Fri, 17 Sep 2021 07:23:38 -0700 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.173) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2242.12; Fri, 17 Sep 2021 07:23:38 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bkVqlZ5iAAmFfb6D2xPNtkPHdj6STdI5MpDGN4YSSnkiNmK2PnfGGdvvZAiHX6ZSFXbf/1bwKN/PP7dDDpy9IG5SsggeeRHmAR9EmcVbXz5RzcNVmMRhvlYd81SLPs2hmx1fl/ISgyw3XNNSpzVUMH4mP4NrXA7FqOjXXCI7BR6eXgQtHZwdyO+SPj39785pVtYZbNE6fWlMjSPnZA33yg6My5KCJ8x0KfdMojoGS91WsbhKaFInLzaC8D02ji2UDHrWfA+9sq61fJNvkUl5tfMKDZFFYB/+8nxJKyjpidmXCRBErejHv+xgNa4WUd6il3mDWJNW7qfTocYafJmhXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=w9fy/mtxg5zBfmwMUWUwfS39rBQ/WXJlylPLFVdPJYw=; b=e8EnRy3dM6Enq2niZPVdCQIW6SS+XPpweTKwUSOXKeu5SZ8Y7KKldupsUw8qKwEWT4S5/pNLsdf8qyJjxVTcb4cdzH9zmNjPVi/O43Rl+T9zd66phzBcFE67uQeHj6bGL29jrb3w++6t08MxAKSFA6R4KgqaryniVF3TxPtPHdi3efiZqaYOtq43AfwLXoUwMnRWmc85RCrAUcKIKAQGr1gjWc5lbgWuuidgibJZv0xFYle+sFuELLNz/wd3e4T5doyCOpCjz+5lqo7FmihZC2waPSmTdjhXjx16lIKJSyi6nVt/ZnIiUZOjWzEj03bXxxk+0eVXrR/16MljtmAxPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w9fy/mtxg5zBfmwMUWUwfS39rBQ/WXJlylPLFVdPJYw=; b=dmzuTEbGfM721RdvH/OgtibXDfCJd/qRE+iJ387vH8sYBqJOiHgjMM2wquPCWPXf0SCuZPui/Coq6hKlbqgiPlsb5jjEsy8mCtcbAVWPsYKnbozjaRKvaLJ6zhdT6WzvKe2pXZ+NqOk0ob5GWhSzkVRLLTh5xRpCrck0xoRfR9g= Received: from BY5PR11MB4451.namprd11.prod.outlook.com (2603:10b6:a03:1cb::30) by SJ0PR11MB5152.namprd11.prod.outlook.com (2603:10b6:a03:2ae::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4523.14; Fri, 17 Sep 2021 14:23:37 +0000 Received: from BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::e905:54de:a94a:dfa8]) by BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::e905:54de:a94a:dfa8%5]) with mapi id 15.20.4523.016; Fri, 17 Sep 2021 14:23:37 +0000 From: "Chautru, Nicolas" To: Nipun Gupta , "dev@dpdk.org" , "gakhil@marvell.com" CC: "david.marchand@redhat.com" , Hemant Agrawal , Tom Rix Thread-Topic: [PATCH v5 1/9] bbdev: add big endian processing data capability Thread-Index: AQHXp8/qWmQWjx/GoEOAq8ATtEm/xauiTFQggAWgi4CAAGHyQA== Date: Fri, 17 Sep 2021 14:23:36 +0000 Message-ID: References: <20210318063421.14895-1-hemant.agrawal@nxp.com> <20210912121510.22699-1-nipun.gupta@nxp.com> <20210912121510.22699-2-nipun.gupta@nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0e684232-32d3-49d6-0d16-08d979e6bd0a x-ms-traffictypediagnostic: SJ0PR11MB5152: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4714; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: xrbV0O/fB+ZphX1th7nobEMyBgX7BF1/HO0VRCTRLInT9UMySwwO7YVUQyKrLZ2OVDgD/gc2Mwq/20qjyay6SGUTfCMFwVYFf2gahpuhWDw4cPHD6JcykDrmgT3lIuBZxl2yRSF1hxjnIe42/0x6xcx154s+PBWBEMGMBz1HHJdq4bIWvqND5vAO2PZ6nRhfQcaGCsSEV0V/RYzYHsqcrF2oag8DVIDO1P14mplT9uuy2yykysRGW25BGQZvNxuTrzIB4DwoNea3D70w43RUpQW2jjs7ITKxUbcrceXs+Ne3XmlrvK0BXp5ZisfCwWEalDC/+nk8ZTpP5rmRcl8KFhegJeGGG4riAG2yRMukTPIehA5PoSMej5hE6Jc5Jm2H9NGHQFBBwa46/AHs/DwvwKhU6OLYEvBOs0hubuNSQVbO8bKpvfYkhe2Ihga6AUlgRBckrSqjAcUkIw0C3/nWAXlQL2Zv8faBITUK6ymvN2+MOsPUMMqaGG0I1qWlF9AP7+DQVpeSFGKBcKAACy6PSphdcuwOSGYwYsw6N5zeR+T9uu5KU0w0uUSqvmOfxdT9dRqYldhCF3Ac9ND7V5DTbclDfLQzh8ClY/K9Nmku2qCFLLWoFiBZepo/8xq/LWfLDsDe3x3ib25F8udFH1NR3Wrx4LoKQkp0W+C8k+GLnMcCqW8/g0cyFghGNNXObO+2hAWWQJWGc0t/qE7Fw11cQQ== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BY5PR11MB4451.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(33656002)(186003)(8936002)(53546011)(54906003)(8676002)(52536014)(71200400001)(6506007)(110136005)(4326008)(5660300002)(316002)(508600001)(7696005)(38100700002)(9686003)(38070700005)(26005)(76116006)(55016002)(2906002)(66556008)(66446008)(64756008)(66476007)(83380400001)(66946007)(122000001)(86362001); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?y65A/vStkzdBDD1Jk8f3RGIfPAnoec/1yqPm2dUEwqIIZEqqYn2NHPFh4JWn?= =?us-ascii?Q?N/fQ9BW9OQQnt8jLGAHHnhMn0VC4MwsZhx43IQ612OVZQhZo/UFcVC2hkVhc?= =?us-ascii?Q?8KEDRivzF90KT1XDmq92HER3wypkurzYNAsfxNFXAma8T+mlAY0y9NnQcXrm?= =?us-ascii?Q?2wQG2G9m0re3/iW7kZl6b9XZjergaSi2Yn7j34344ruon57rprJ1wHecD/Ds?= =?us-ascii?Q?kukASMsmw+FPt9neMR9oFApDiaf5qXpIHYTmrfeUVrDZRIY1w6qSVSZF4bDE?= =?us-ascii?Q?L2LkRhzgRupk8hOhoU6pK5/PVNQ13+9oUjF5lKV8t2t8PATp1g47vjHH/ahw?= =?us-ascii?Q?3Jp/qeF26k7M8CqhMUMWU2IGiWBeXwew1TExSBfS9BOdIphfAc+6rwu3Sjn8?= =?us-ascii?Q?PxAYkI5sbwNQSU6VHXSJ9ngZfm1lVa+DlL/Xzew0P2U4M6AHlSF3IQ5yZ1Fo?= =?us-ascii?Q?k8HJ6707ees0fi7inFqyyQQGJ9adbHXosRO3nTagV9Ej906UvzscEks2ntWH?= =?us-ascii?Q?NjCCJFvVvXL3XoFrn4bpgejs5jxDtIR4WoQD3aBBgUig35LkbYxQCxkcLvmg?= =?us-ascii?Q?ize0T3I3dKkAMrChsQzC/X6zTM1zPBJwl4uNkXdOz0tMogx1fKis9k1OeM7Q?= =?us-ascii?Q?ZYa2y+6cH3qSUvwZN4Ghfi9rLKLbTHz+H2rEQzBCIPHlDQ30dSsoY5Aduz4P?= =?us-ascii?Q?0ajGQqnVOhdLBGEQ5lbMxSejyo7cLjfdXRFNf+B6OX1+bXdsGM6hyfrkDUkg?= =?us-ascii?Q?R56ccvXlUlkbl4WJ8Y8gmIqkKXrHOa27uO0NLty+em3EJdP/sBBni9LqSb8e?= =?us-ascii?Q?6Q8Wp02EwGxcMJC1DOEPlmqbQNAiubIoNuG/VR5pruv6btlbq7xmraRDs5k7?= =?us-ascii?Q?dOW8VXORovA5ypmUUaXc1VNJWkY4IwIHg6CaFWN72ni4y52K3VIKyylwnArK?= =?us-ascii?Q?rJExHVbeTN4gm5Eq5ttrqp7w5YB/zTEUgVt1ofKY6zAp0JsJL9NRSaqvTaUk?= =?us-ascii?Q?W1UMoU1x3X3TxTFTEYU6BZJEMTE+khv6egTSgZmrA0CMlYw9shvpxl9U2dT1?= =?us-ascii?Q?T4etvawSEM0kEC4aGABNXUNOQ4OIwLM8dPp8eJSBS4mq57y641SlPxESDqJJ?= =?us-ascii?Q?Rz1EKZoSqPO66rZHfaVA5I7zLFY5rKKucofO63WcXRMT0hPwlBChTgzWyp0b?= =?us-ascii?Q?NoMUqYrGoyHfooRGy39NLaxJ5/QiLzpvTiP172VTCFAwTb8Ve9tejPoUZou2?= =?us-ascii?Q?bazU/SlRleQzDWGOVfFfJrBm2Y5vhN4XMVNpiTLWQIJ3MYjPyzGzPI7Dotw9?= =?us-ascii?Q?yg0W+z6acGzXVx//+XC3tuDv?= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0e684232-32d3-49d6-0d16-08d979e6bd0a X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Sep 2021 14:23:36.9378 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: llIcXH7JD67mnfOJao7ebmgkNEVEzwJ+uGxJ50ZUNN7Fb0FUmAVvJpiDRbMOfedHfGxC8nl5ulCCr+dBHOxOxh8LmgVmQ2MbJZHJ4/06Fw0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5152 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 1/9] bbdev: add big endian processing data capability X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Nipun Gupta > Sent: Friday, September 17, 2021 1:30 AM > To: Chautru, Nicolas ; dev@dpdk.org; > gakhil@marvell.com > Cc: david.marchand@redhat.com; Hemant Agrawal > ; Tom Rix > Subject: RE: [PATCH v5 1/9] bbdev: add big endian processing data capabil= ity >=20 >=20 >=20 > > -----Original Message----- > > From: Chautru, Nicolas > > Sent: Tuesday, September 14, 2021 12:10 AM > > To: Nipun Gupta ; dev@dpdk.org; > > gakhil@marvell.com > > Cc: david.marchand@redhat.com; Hemant Agrawal > > ; Tom Rix > > Subject: RE: [PATCH v5 1/9] bbdev: add big endian processing data > > capability > > > > > > > > > -----Original Message----- > > > From: Nipun Gupta > > > Sent: Sunday, September 12, 2021 5:15 AM > > > To: dev@dpdk.org; gakhil@marvell.com; Chautru, Nicolas > > > > > > Cc: david.marchand@redhat.com; hemant.agrawal@nxp.com; Nipun > Gupta > > > > > > Subject: [PATCH v5 1/9] bbdev: add big endian processing data > > > capability > > > > > > This patch intoduces a new capability of the bbdev device to process > > > the LDPC data in big endian order. > > > > Hi Gupta, > > > > As mentioned in previous patch iteration earlier this year I believe > > this is not really an operation flag but more a different device capabi= lity. > > ie. you would have the same formalism for all operation (5GDL, 5GUL, > > 4GDL, ...) for that PMD/hw and that is not something you will change > > dynamically as an option. > > I would suggest to add this under "struct rte_bbdev_driver_info" which > > can be used to capture device specific capability and information. In > > term of processing and operation, everything is the same except > > endianness assumption for the input/output data. >=20 > Okay, it can be done this way. Then it would be assumption of the driver, > that the operation is in the format as per the driver info. Ill change it= in > respin. Yes the fact that the capability is exposed out means that this is the resp= onsibility of the application to provide input data in that format (ie. sim= ilar as for llr numerical representation). The endianness switch can be done in bbdev-test so that all existing vector= s can be run seamlessly even on your PMD (ie. different endianness than the= default one so far). >=20 > > > > > > > > > > Signed-off-by: Hemant Agrawal > > > Signed-off-by: Nipun Gupta > > > --- > > > doc/guides/bbdevs/features/default.ini | 1 + > > > doc/guides/prog_guide/bbdev.rst | 6 ++++++ > > > lib/bbdev/rte_bbdev_op.h | 14 ++++++++++++-- > > > 3 files changed, 19 insertions(+), 2 deletions(-) > > > > > > diff --git a/doc/guides/bbdevs/features/default.ini > > > b/doc/guides/bbdevs/features/default.ini > > > index 5fe267a625..ae5aacf8f7 100644 > > > --- a/doc/guides/bbdevs/features/default.ini > > > +++ b/doc/guides/bbdevs/features/default.ini > > > @@ -14,3 +14,4 @@ LLR/HARQ Compression =3D > > > External DDR Access =3D > > > HW Accelerated =3D > > > BBDEV API =3D > > > +Big Endian Processing =3D > > > diff --git a/doc/guides/prog_guide/bbdev.rst > > > b/doc/guides/prog_guide/bbdev.rst index 9619280ffc..6540b514bb > > > 100644 > > > --- a/doc/guides/prog_guide/bbdev.rst > > > +++ b/doc/guides/prog_guide/bbdev.rst > > > @@ -747,6 +747,9 @@ given below. > > > |RTE_BBDEV_LDPC_ENC_CONCATENATION = | > > > | Set if a device supports concatenation of non byte aligned output > > > | +------ > > > --------------------------------------------------------------+ > > > +|RTE_BBDEV_LDPC_ENC_BIG_ENDIAN = | > > > +| Set if a device supports Big Endian data processing = | > > > ++-------------------------------------------------------------------= -+ > > > > > > The structure passed for each LDPC encode operation is given below, > > > with the operation flags forming a bitmask in the ``op_flags`` field. > > > @@ -942,6 +945,9 @@ given below. > > > |RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK > | > > > | Set if a device supports loopback access to HARQ internal memory = | > > > > > > +------------------------------------------------------------------- > > > -+ > > > +|RTE_BBDEV_LDPC_DEC_BIG_ENDIAN = | > > > +| Set if a device supports Big Endian data processing = | > > > ++-------------------------------------------------------------------= -+ > > > > > > The structure passed for each LDPC decode operation is given below, > > > with the operation flags forming a bitmask in the ``op_flags`` field. > > > diff --git a/lib/bbdev/rte_bbdev_op.h b/lib/bbdev/rte_bbdev_op.h > > > index f946842727..9e9b5be81f 100644 > > > --- a/lib/bbdev/rte_bbdev_op.h > > > +++ b/lib/bbdev/rte_bbdev_op.h > > > @@ -186,7 +186,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks { > > > * for HARQ memory. If not set, it is assumed the filler bits are = not > > > * in HARQ memory and handled directly by the LDPC decoder. > > > */ > > > - RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS =3D (1ULL << > > > 18) > > > + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS =3D (1ULL << > > > 18), > > > + /** Set if a device supports Big Endian data processing. > > > + * If not set Little Endian data processing is supported by > > > + * default. > > > + */ > > > + RTE_BBDEV_LDPC_DEC_BIG_ENDIAN =3D (1ULL << 8) > > > }; > > > > > > /** Flags for LDPC encoder operation and capability structure */ @@ > > > -206,7 > > > +211,12 @@ enum rte_bbdev_op_ldpcenc_flag_bitmasks { > > > /** Set if a device supports scatter-gather functionality. */ > > > RTE_BBDEV_LDPC_ENC_SCATTER_GATHER =3D (1ULL << 6), > > > /** Set if a device supports concatenation of non byte aligned > > > output */ > > > - RTE_BBDEV_LDPC_ENC_CONCATENATION =3D (1ULL << 7) > > > + RTE_BBDEV_LDPC_ENC_CONCATENATION =3D (1ULL << 7), > > > + /** Set if a device supports Big Endian data processing > > > + * If not set Little Endian data processing is supported by > > > + * default. > > > + */ > > > + RTE_BBDEV_LDPC_ENC_BIG_ENDIAN =3D (1ULL << 8) > > > }; > > > > > > /** Flags for the Code Block/Transport block mode */ > > > -- > > > 2.17.1