From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB41BA04BA; Fri, 2 Oct 2020 10:25:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 17D5C1D58D; Fri, 2 Oct 2020 10:25:52 +0200 (CEST) Received: from nat-hk.nvidia.com (nat-hk.nvidia.com [203.18.50.4]) by dpdk.org (Postfix) with ESMTP id 038BE1D53C for ; Fri, 2 Oct 2020 10:25:49 +0200 (CEST) Received: from HKMAIL104.nvidia.com (Not Verified[10.18.92.77]) by nat-hk.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 02 Oct 2020 16:25:47 +0800 Received: from HKMAIL104.nvidia.com (10.18.16.13) by HKMAIL104.nvidia.com (10.18.16.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 2 Oct 2020 08:25:47 +0000 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.176) by HKMAIL104.nvidia.com (10.18.16.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 2 Oct 2020 08:25:46 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fzKyntLZVi8ZvPzdIZhgmCcobZnRPW3FnsMSg/wg0HndO4ZGR7CeRdmu7MEA2mfXbk5elfElO73roSj1bvi6tIQeEqYsxZnulMoQUfIYDRcK17xSn7ovisAxzRkNfraOxPiRrct2Pa+QVzE2PkWU5tm2IaE6dq5sg0rBJY9BiN5zxqqhwZ7ADqqlaG3vupWB+uu4wIkSXx6uVaLsBa2/HFclL6utdL5OmfGKEETuYV5kDLZ+4kjYD1MMiRVepV2XigTt0Tx8kKYJQv24zkuPWm51u1HLsZ6wB/sbpskqLnD62ZZtVZMDaQa12p+joR74eShwTBhJ+bWGdk4I/RAHDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=J36X+Uxw4/f/aBnDwMRDeg8a2L+T6VbKsifpEbas3wE=; b=Cp4bYX19H0t74bOu+yHDK2dJao8G/C+gItZVg6iHlxFniRguRgTaQsG6AJs4Gh6ptFY2zLnlDDYZq3zVX0AY5hRBFcnZpTQ7EU3LwsqxVJ9AjdSsyIbu7SC0i8bcSFKwsL6DvdIw9I3X2PBG3tjbIqhki98aGf40K1lqPWGImh2Aj3ubx6IED24jI6y/ocPlFTHMviVxvoh0bpF+JelTMvUSzUnZ86NdQuVc6lIg0+DqYhgssxOq+yLjQaqDKW/qaVtz16jIlvupv+qkgKO9bVIPe/t4DkyJwN4kbB+Z4hzCegIVxgG0oDWzBsezZ1PJVXyeMEuNVIKNrctLM6i3dA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from BY5PR12MB4083.namprd12.prod.outlook.com (2603:10b6:a03:20d::18) by BY5PR12MB5014.namprd12.prod.outlook.com (2603:10b6:a03:1c4::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.34; Fri, 2 Oct 2020 08:25:45 +0000 Received: from BY5PR12MB4083.namprd12.prod.outlook.com ([fe80::a400:8245:883c:5c9d]) by BY5PR12MB4083.namprd12.prod.outlook.com ([fe80::a400:8245:883c:5c9d%7]) with mapi id 15.20.3433.038; Fri, 2 Oct 2020 08:25:45 +0000 From: Li Zhang To: Ori Kam , Dekel Peled , "Slava Ovsiienko" , Matan Azrad CC: "dev@dpdk.org" , NBU-Contact-Thomas Monjalon , Raslan Darawsheh Thread-Topic: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP identifier fields Thread-Index: AQHWl0l/wFcb9FsVUkiwYdLI0luxo6mCZvOAgAGUj3A= Date: Fri, 2 Oct 2020 08:25:44 +0000 Message-ID: References: <20200928033813.22112-1-lizh@nvidia.com> <20200930164734.23675-1-lizh@nvidia.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [40.81.203.179] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cd81bb76-5ac7-4be5-46a0-08d866acc22d x-ms-traffictypediagnostic: BY5PR12MB5014: x-ld-processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: eQRPref6SGY0niWzHUe+ZGcwR0340qF6yokgWkGSpxTihvQeSDQYcqhgFr8ZHg+7Om0A0LuhuyIX6K5+eImZMTDwOMFBtj/WLIZDez9tRyzCK1AXAh6cMtm7UOF9Loa51tFWydqUuiCgDmGMBdfx+rLlq1wTGDRWBWUajn0JXGLMDEZODGqtPlWYojbSs6dj1eJL1CCPK6e28TeZn2pIGoKs6mjptnH12EMHpAFr2dvS4EdKwDcN+W6eYfluxrjKZxfquo3/42xX4eBRjnFKTqyDiOCDF0aSzprjFEEC0gr6smyqW+Pc3xH3g5AMP5xTVDr2LYUbpTkJUn3grd6mbg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BY5PR12MB4083.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(136003)(346002)(366004)(396003)(39860400002)(376002)(7696005)(4326008)(66946007)(86362001)(33656002)(83380400001)(66446008)(66556008)(64756008)(66476007)(71200400001)(9686003)(186003)(8936002)(76116006)(5660300002)(26005)(2906002)(55016002)(478600001)(110136005)(107886003)(54906003)(53546011)(6506007)(316002)(6636002)(52536014); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: L5XtWxlK/VdaOu3Q39q/Xiv4Lx9dLU3k6DoFmF950uqFgiD4fe/1kz2AQL1De+h9Ct8BZ9OIRphAlgAEYSwz3cugTsS0kX0sZi/MB8+OV6aHWOoQ4L++CDsTgvZPLLF18y70Sb32zDPBCle/kLaU9zFZrvrA5AvlqaKvZWYQm4vg5WDiFW7B4E1TcDBvBTBnKAzZ4uAa+ZqXt7Giie/QbvLBFcxlSeZLaJ+mQLsFP1aa8VKj3u1mHb7nKRt2Eu1yFYtAjirfdAk3RsSfONunlti1lst0GRAILXJW2KwtRU/SLY+dIGIHufKpQJGpK6TvGfVx7KrUZ2suNHWX5IKBhjAww6g1/Ne8XhoD/VFSszE2iJ8lt05KJD0iTIWbZeFvYJT1QC1dV45lu4+hfOGX2kwNfUs1oUZ+aHaPCq4b0nA5U/seDX18TvqPveNvRopND+QkCdEnGPOtl5qrICy4WgR+G50MsI5zBBKyMPG3d1YIefnawvcl4ArdLhQTxzL+g5V1ewS4Vq5NuaqWm8dF6DqO0tRqBsxTvM9ZNJZDqCDQ+MP1FkdQ92wDNdWOOr7Ry4sQAo9HvGnisFL+s+FpXuYZ8GV15mf/6Y/jPqnffhbb4ov6EtFpasSeKhO6joWD5h/jubX2T30hAMQC/rOvJA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB4083.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd81bb76-5ac7-4be5-46a0-08d866acc22d X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Oct 2020 08:25:44.8242 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Ecb3e8gAtPa1Kpydbg3CAlg+10LGcTmWF7UoIKThkpN2SmMhBxZvtcggShFUSFyR X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5014 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1601627147; bh=J36X+Uxw4/f/aBnDwMRDeg8a2L+T6VbKsifpEbas3wE=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To: CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References: In-Reply-To:Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ld-processed: x-ms-exchange-transport-forked:x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers:x-ms-exchange-senderadcheck: x-microsoft-antispam:x-microsoft-antispam-message-info: x-forefront-antispam-report:x-ms-exchange-antispam-messagedata: Content-Type:Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=SbCjWy4JyUYwWVYfHDM1Bz+vWJOlcGpuMhKOjuFgEUIFBbBHa3PgF6dh8IY9D8hJe RR6DN/9VRQMPHGy6HY0dkdsokgV+MMTUdsQ0K5/1XppXIscSnhLtSAp2fPPpUp33VI /ng7MmVwc0e8QHxpV9wKXSpYdrIECZzJ9tCedbQDReX6me+Fn05TQO/yMmazl4aYXq 8/Dp3bDv8KPNRm+C7Guf0C/c02h6tJUpkUJENC8KXWZZo/dNz7zM+sma6H7aUeIVP+ 2cUa8cgwM/6E3vOAAOirSXqnikATu2LHgmT57+C0aa85I8atnBj0HW6xOskE00leF/ SgvzE0ONDMFOg== Subject: Re: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP identifier fields X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Ori, Thanks for your comments. My answer inline. I will update them in V4 patch. Regards, Li Zhang > -----Original Message----- > From: Ori Kam > Sent: Thursday, October 1, 2020 4:14 PM > To: Li Zhang ; Dekel Peled ; Slava > Ovsiienko ; Matan Azrad > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > ; Raslan Darawsheh > Subject: RE: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP > identifier fields >=20 > Hi > Sorry I didn't see that you sent V3 and responded on V2 So just rewriting= my > comments. >=20 > Best, > Ori >=20 > > -----Original Message----- > > From: dev On Behalf Of Li Zhang > > Subject: [dpdk-dev] [PATCH v3 1/1] net/mlx5: support match ICMP > > identifier fields > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > Update ICMP mask parameter with ICMP identifier and sequence number > > fields. > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are > set. > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > Signed-off-by: Li Zhang > > --- > > doc/guides/nics/mlx5.rst | 4 ++-- > > doc/guides/rel_notes/release_20_11.rst | 2 +- > > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > > drivers/net/mlx5/mlx5_flow_dv.c | 16 +++++++++++++++- > > 4 files changed, 26 insertions(+), 6 deletions(-) > > > > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index > > 211c0c5a6c..576dbe5efd 100644 > > --- a/doc/guides/nics/mlx5.rst > > +++ b/doc/guides/nics/mlx5.rst > > @@ -288,7 +288,7 @@ Limitations > > - The input buffer, providing the removal size, is not validated. > > - The buffer size must match the length of the headers to be removed= . > > > > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are > > all > > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > > +matching, > > IP-in-IP and MPLS flow matching are all > > mutually exclusive features which cannot be supported together > > (see :ref:`mlx5_firmware_config`). > > > > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. > > > > FLEX_PARSER_PROFILE_ENABLE=3D1 > > > > -- enable ICMP/ICMP6 code/type fields matching:: > > +- enable ICMP(code/type/identifier/sequence number) / > > +ICMP6(code/type) > > fields matching:: > > > > FLEX_PARSER_PROFILE_ENABLE=3D2 > > > > diff --git a/doc/guides/rel_notes/release_20_11.rst > > b/doc/guides/rel_notes/release_20_11.rst > > index c6642f5f94..791f133d8f 100644 > > --- a/doc/guides/rel_notes/release_20_11.rst > > +++ b/doc/guides/rel_notes/release_20_11.rst > > @@ -73,7 +73,7 @@ New Features > > * Added flag action. > > * Added raw encap/decap actions. > > * Added VXLAN encap/decap actions. > > - * Added ICMP and ICMP6 matching items. > > + * Added ICMP(code/type/identifier/sequence number) and > > ICMP6(code/type) matching items. > > * Added option to set port mask for insertion/deletion: > > ``--portmask=3DN`` > > where N represents the hexadecimal bitmask of ports used. > > diff --git a/drivers/net/mlx5/mlx5_flow.c > > b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 > > --- a/drivers/net/mlx5/mlx5_flow.c > > +++ b/drivers/net/mlx5/mlx5_flow.c > > @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct > > rte_flow_item *item, > > struct rte_flow_error *error) { > > const struct rte_flow_item_icmp *mask =3D item->mask; > > + const struct rte_flow_item_icmp nic_mask =3D { > > + .hdr.icmp_type =3D 0xff, > > + .hdr.icmp_code =3D 0xff, > > + .hdr.icmp_ident =3D RTE_BE16(0xffff), > > + .hdr.icmp_seq_nb =3D RTE_BE16(0xffff), > > + }; > > const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > > const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > @@ -1325,10 +1331,10 @@ > > mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > > RTE_FLOW_ERROR_TYPE_ITEM, > > item, > > "multiple L4 layers not supported"); > > if (!mask) > > - mask =3D &rte_flow_item_icmp_mask; > > + mask =3D &nic_mask; > > ret =3D mlx5_flow_item_acceptable > > (item, (const uint8_t *)mask, > > - (const uint8_t *)&rte_flow_item_icmp_mask, > > + (const uint8_t *)&nic_mask, > > sizeof(struct rte_flow_item_icmp), error); > > if (ret < 0) > > return ret; > > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > > b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..b5d6455067 > 100644 > > --- a/drivers/net/mlx5/mlx5_flow_dv.c > > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > > @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, > void > > *key, { > > const struct rte_flow_item_icmp *icmp_m =3D item->mask; > > const struct rte_flow_item_icmp *icmp_v =3D item->spec; > > + uint32_t icmp_header_data_m =3D 0; > > + uint32_t icmp_header_data_v =3D 0; > > void *headers_m; > > void *headers_v; > > void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, @@ - > 7396,8 > > +7398,14 @@ flow_dv_translate_item_icmp(void *matcher, void *key, > > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > > IPPROTO_ICMP); > > if (!icmp_v) > > return; > > - if (!icmp_m) > > + if (!icmp_m) { > > icmp_m =3D &rte_flow_item_icmp_mask; > > + icmp_header_data_m =3D RTE_BE32(UINT32_MAX); > > + } else { > > + icmp_header_data_m =3D rte_cpu_to_be_16(icmp_m- > > >hdr.icmp_seq_nb); > > + icmp_header_data_m |=3D > > + rte_cpu_to_be_16(icmp_m->hdr.icmp_ident) << 16; > > + } >=20 > Yes but there is no need to add new fields to the mask, it will break exi= sting > applications. > So please remove it. >=20 Thanks, I will remove &rte_flow_item_icmp_mask. For icmp_header_data_m, it is used to merge 16bit icmp_seq_nb and 16bit icm= p_ident into 32bit data. So that it can use icmp_header_data_m set 32bit misc3_m directly.=20 > > /* > > * Force flow only to match the non-fragmented IPv4 ICMP packets. > > * If only the protocol is specified, no need to match the frag. > > @@ -7412,6 +7420,12 @@ flow_dv_translate_item_icmp(void *matcher, > void > > *key, > > icmp_m->hdr.icmp_code); > > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > > + icmp_header_data_v =3D rte_cpu_to_be_16(icmp_v- > >hdr.icmp_seq_nb); > > + icmp_header_data_v |=3D rte_cpu_to_be_16(icmp_v->hdr.icmp_ident) > > << 16; >=20 > Why is it not BE? From the structure definition: > struct rte_icmp_hdr { > uint8_t icmp_type; /* ICMP packet type. */ > uint8_t icmp_code; /* ICMP packet code. */ > rte_be16_t icmp_cksum; /* ICMP packet checksum. */ > rte_be16_t icmp_ident; /* ICMP packet identifier. */ > rte_be16_t icmp_seq_nb; /* ICMP packet sequence number. */ } > __rte_packed; Also you are setting cpu value with BE. > Maybe you want to rte_be_to_cpu? >=20 You are right I should use the rte_be_to_cpu_16 instead of rte_cpu_to_be_16= . > > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, > > + icmp_header_data_m); > > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, > > + icmp_header_data_v & icmp_header_data_m); > > } > > > > /** > > -- > > 2.21.0