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Wed, 22 Jul 2020 08:26:48 +0000 Received: from BYAPR11MB2935.namprd11.prod.outlook.com ([fe80::d514:54b4:8e58:2061]) by BYAPR11MB2935.namprd11.prod.outlook.com ([fe80::d514:54b4:8e58:2061%3]) with mapi id 15.20.3195.026; Wed, 22 Jul 2020 08:26:48 +0000 From: "Dumitrescu, Cristian" To: "Xu, Ting" , "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH v4] lib/table: fix cache alignment issue Thread-Index: AQHWX82i+KTf+DtoXESWs1iJ7M+JEakTQuIA Date: Wed, 22 Jul 2020 08:26:48 +0000 Message-ID: References: <20200616162705.83575-1-ting.xu@intel.com> <20200722021628.17194-1-ting.xu@intel.com> In-Reply-To: <20200722021628.17194-1-ting.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.79.55.254] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 94b91c8d-bb07-4c47-3969-08d82e18fa49 x-ms-traffictypediagnostic: BY5PR11MB3943: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB2935.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 94b91c8d-bb07-4c47-3969-08d82e18fa49 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jul 2020 08:26:48.3922 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MjBgqhdIbZY2kHfuHpRlun8N6ch3Yh6qX+ADMIB78YiDBg9WttPNBR6UqbtW5Z09rg0DXxDOCMrJn7komEV8UyJHc5vxpXfRek5D3EU9wEw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3943 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v4] lib/table: fix cache alignment issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > +#ifdef RTE_ARCH_64 > struct rte_bucket_4_32 { > /* Cache line 0 */ > uint64_t signature[4 + 1]; > @@ -46,6 +47,22 @@ struct rte_bucket_4_32 { > /* Cache line 3 */ > uint8_t data[0]; > }; > +#else > +struct rte_bucket_4_32 { > + /* Cache line 0 */ > + uint64_t signature[4 + 1]; > + uint64_t lru_list; > + struct rte_bucket_4_32 *next; > + uint32_t pad; > + uint64_t next_valid; > + > + /* Cache lines 1 and 2 */ > + uint64_t key[4][4]; > + > + /* Cache line 3 */ > + uint8_t data[0]; > +}; > +#endif >=20 Hi Ting, Yes, it looks good, but as mentioned previously please do the same on the o= ther files in the same folder and add the changes to your patch, as we need= to keep all these files in sync: rte_table_hash_key8.c, struct rte_bucket_4_8 rte_table_hash_key32.c, struct rte_bucket_4_32 Thanks, Cristian