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Mon, 14 Sep 2020 08:12:24 +0000 Received: from BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::25c7:1828:b871:bb8]) by BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::25c7:1828:b871:bb8%6]) with mapi id 15.20.3370.019; Mon, 14 Sep 2020 08:12:24 +0000 From: "Van Haaren, Harry" To: Pavan Nikhilesh Bhagavatula , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant Thread-Index: AQHWiBx431Rywk96Y0Wlfep4uWMH0KlnA88AgADEyVA= Date: Mon, 14 Sep 2020 08:12:23 +0000 Message-ID: References: <20200911091919.62167-1-harry.van.haaren@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [87.198.126.230] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cc7ad9b3-247b-40cd-8324-08d85885e946 x-ms-traffictypediagnostic: BYAPR11MB3238: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3044; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3143.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc7ad9b3-247b-40cd-8324-08d85885e946 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2020 08:12:23.9113 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Fgaad0RLCNtVdXgqUdA0Gr3VGFG8LxaOoyKcWrWrcjwwJeNGx9ETWwwg6DElT0CnLPgrmiDa4GMt0vj6eABDcgPeGC0UwF+AxR7YvJEB0zI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3238 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pavan Nikhilesh Bhagavatula > Sent: Sunday, September 13, 2020 9:11 PM > To: Van Haaren, Harry ; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant >=20 > >This commit adds a new rte_prefetch0_write() variant, suggests to the > >compiler to use a prefetch instruction with intention to write. As a > >compiler builtin, the compiler can choose based on compilation target > >what the best implementation for this instruction is. >=20 > Why not have the other variants too i.e. l2/l3/temporal store prefetches = too? Hi Pavan, Are there architectures that actually implement those? Usually for a WB mem= store to complete, the data must be present in L1 cache (on x86 at least), and that's what the= patch below with write0 achieves. I'm against adding all the variants "just in case", it leads to API bloat, = and increases cognitive load on the programmer. My expectation is that in 99% of usage th= e prefetch write instruction should target L1. Cheers, -Harry > >Signed-off-by: Harry van Haaren > > > >--- > > > >The integer constants passed to the builtin are not available as > >a #define value, and doing #defines just for this write variant > >does not seems a nice solution to me... particularly for those using > >IDEs where any #define value is auto-hinted for code-completion. > > > >--- > > lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+)