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From: "Sevincer, Abdullah" <abdullah.sevincer@intel.com>
To: Chenbo Xia <chenbox@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	"jerinj@marvell.com" <jerinj@marvell.com>,
	 "Chen, Mike Ximing" <mike.ximing.chen@intel.com>,
	"Richardson, Bruce" <bruce.richardson@intel.com>,
	"NBU-Contact-Thomas Monjalon (EXTERNAL)" <thomas@monjalon.net>,
	"ruifeng.wang@arm.com" <ruifeng.wang@arm.com>
Subject: RE: [PATCH v6 1/2] bus/pci: add function to enable/disable PASID
Date: Mon, 6 Nov 2023 15:44:35 +0000	[thread overview]
Message-ID: <BYAPR11MB31587F40A1B34C18D401C55FE9AAA@BYAPR11MB3158.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CF1C410F-846C-42D5-8959-75D4BA18715A@nvidia.com>


>+Is PASID now part of PCIe spec? This APIs should both work for x86/arm?
>+Not sure ARM is OK with the naming, previously they are calling it more as Sub Stream ID (SSID)
For reference, Look for PASID definitions in the PCIe spec.
The API takes in offset which might be different for other devices. Part of the reason why we defined the API this way.

>+Align with old definitions will looks better. Using TAB?
I will align.

For v7 I will use naming rte_pci_pasid_set_state, is everyone okay with that?

Thanks.
Abdullah.


  reply	other threads:[~2023-11-06 15:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-03 18:29 [PATCH v6 0/2] *** Disable PASID for DLB Device *** Abdullah Sevincer
2023-11-03 18:29 ` [PATCH v6 1/2] bus/pci: add function to enable/disable PASID Abdullah Sevincer
2023-11-04  7:32   ` Jerin Jacob
2023-11-04  9:19     ` Thomas Monjalon
2023-11-05  5:48       ` Jerin Jacob
2023-11-04 14:01   ` Bruce Richardson
2023-11-05  5:43     ` Jerin Jacob
2023-11-06  1:16   ` Chenbo Xia
2023-11-06 15:44     ` Sevincer, Abdullah [this message]
2023-11-07  8:17     ` Ruifeng Wang
2023-11-03 18:29 ` [PATCH v6 2/2] event/dlb2: fix disable PASID Abdullah Sevincer

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