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Thu, 8 Oct 2020 15:21:59 +0000 From: "Ananyev, Konstantin" To: "Power, Ciara" , "dev@dpdk.org" CC: "Power, Ciara" , "Xing, Beilei" , "Guo, Jia" Thread-Topic: [dpdk-dev] [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth Thread-Index: AQHWlysGOdS8rFjjEU20GAGWxR5PoamN3bUQ Date: Thu, 8 Oct 2020 15:21:59 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-5-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-5-ciara.power@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2072d830-3e14-4c54-40e8-08d86b9de688 x-ms-traffictypediagnostic: BYAPR11MB3765: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2072d830-3e14-4c54-40e8-08d86b9de688 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 15:21:59.3422 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fSFneG4LBcFXaA/675rCkIpXvAHKZiRsk+D76FucFfsxwJAbDLMud8728qy527EnpJLpshqEWCWf6uYGeob8tE5fwefGziRNUe0jDjPSYGM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3765 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > When choosing a vector path to take, an extra condition must be > satisfied to ensure the max SIMD bitwidth allows for the CPU enabled > path. >=20 > Cc: Beilei Xing > Cc: Jeff Guo >=20 > Signed-off-by: Ciara Power > --- > drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c > index 60b33d20a1..9b535b52fa 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -3098,7 +3098,8 @@ static eth_rx_burst_t > i40e_get_latest_rx_vec(bool scatter) > { > #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + rte_get_max_simd_bitwidth() >=3D RTE_MAX_256_SIMD) > return scatter ? i40e_recv_scattered_pkts_vec_avx2 : > i40e_recv_pkts_vec_avx2; Hmm, but that means - if user will set --simd-bitwidth=3D128 we'll select s= calar function, right? Even though sse one is available. Is that what we really want in that case? > #endif > @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) > * use of AVX2 version to later plaforms, not all those that could > * theoretically run it. > */ > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && > + rte_get_max_simd_bitwidth() >=3D RTE_MAX_256_SIMD) > return scatter ? i40e_recv_scattered_pkts_vec_avx2 : > i40e_recv_pkts_vec_avx2; > #endif > @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) > } > } >=20 > - if (ad->rx_vec_allowed) { > + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > /* Vec Rx path */ > PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=3D%d.", > dev->data->port_id); > @@ -3268,7 +3271,8 @@ static eth_tx_burst_t > i40e_get_latest_tx_vec(void) > { > #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + rte_get_max_simd_bitwidth() >=3D RTE_MAX_256_SIMD) > return i40e_xmit_pkts_vec_avx2; > #endif > return i40e_xmit_pkts_vec; > @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) > * use of AVX2 version to later plaforms, not all those that could > * theoretically run it. > */ > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && > + rte_get_max_simd_bitwidth() >=3D RTE_MAX_256_SIMD) > return i40e_xmit_pkts_vec_avx2; > #endif > return i40e_xmit_pkts_vec; > @@ -3311,7 +3316,9 @@ i40e_set_tx_function(struct rte_eth_dev *dev) > } >=20 > if (ad->tx_simple_allowed) { > - if (ad->tx_vec_allowed) { > + if (ad->tx_vec_allowed && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); > if (ad->use_latest_vec) > dev->tx_pkt_burst =3D > -- > 2.17.1