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Fri, 17 Jul 2020 11:18:35 +0000 Received: from BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f160:29ab:b8f9:4189]) by BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f160:29ab:b8f9:4189%6]) with mapi id 15.20.3174.026; Fri, 17 Jul 2020 11:18:35 +0000 From: "Ananyev, Konstantin" To: "Nicolau, Radu" , "dev@dpdk.org" CC: "Xing, Beilei" , "Guo, Jia" , "Richardson, Bruce" , "jerinjacobk@gmail.com" , "david.marchand@redhat.com" , "Trahe, Fiona" , "Zhao1, Wei" , "ruifeng.wang@arm.com" Thread-Topic: [PATCH v8 4/4] net/ixgbe: use WC store to update queue tail registers Thread-Index: AQHWXCgcbvdzQ0P38ESnztHMP4x1xKkLn3MA Date: Fri, 17 Jul 2020 11:18:35 +0000 Message-ID: References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> <1594982985-31551-1-git-send-email-radu.nicolau@intel.com> <1594982985-31551-5-git-send-email-radu.nicolau@intel.com> In-Reply-To: <1594982985-31551-5-git-send-email-radu.nicolau@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTZlYzk2ZjUtOTg1MS00MDkxLWFhNjEtNjZkMjIwOTVmYzA4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidWpRcVo1TDNRR2lPNjZ5ZVNPQ1VxSmJaVldaWWVFNnRuNGd5WUJXSXRCQUZldXZzeVl2MSt5K0loMHh5bVh0aiJ9 dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 x-ctpclassification: CTP_NT authentication-results: intel.com; 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PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(136003)(396003)(346002)(366004)(376002)(9686003)(55016002)(86362001)(15650500001)(64756008)(316002)(76116006)(6506007)(478600001)(110136005)(186003)(7696005)(4326008)(8676002)(66476007)(8936002)(26005)(71200400001)(54906003)(66946007)(5660300002)(52536014)(83380400001)(66446008)(66556008)(2906002)(33656002); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: lKbgnMS/a9L7741wzTMt1elVUomImupc8PoEb+4oIi0k6qpQQCR5yrRXkefkvxFbbTIlUpXSpirghO+0mBGhhZkbkl2wmghso6fwH14CpfzPM43xoWn7RLhVO6CLqOUPz3CIzphg9iRbSZJ8Drr2e4yhNdl0+qgxBFq02oHB+OEzMXBt9B/fGj0GWPpovxnGOqsVEMOwsHtPvl06qSu+VWRo4t9j2gsWiV+715P+mYtncsd5U0KzLtSdwvntXzkAjeOpwL4KNAf5uo3GxlHnYEzZTb9JexGRbenKTwU5itotL63zKKy3j1TzT9dhGRpxMW2ZCzE5pO7OldE4eoex00xvepXIzGpdrafObh7J5jqKPnLYfVOe8VMAieqD5fA+kQK/lcQfMZ+0UMaFBxcVbdxbXhEVDpEpKAOP0AKcZeiHEgtwr7iirr8eElbc3ZRjEBJP/bCs2Uh5nu6Hit1Pklb5dg+LP3LbuEbGYJSM0So= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca16bcbf-c883-4299-3999-08d82a432597 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2020 11:18:35.3279 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: y5oEn+UiCpkMlK59SFsCXoMSXiM9P6Qi6kAmS2xOOylw5jcWZph7nCWOOZYNKkbHVAFSUMajVzjlDZcMtGHIBdNQvKk6AzCuunq6aC0PXZI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3559 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v8 4/4] net/ixgbe: use WC store to update queue tail registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Performance improvement: use a write combining store > instead of a regular mmio write to update queue tail > registers. >=20 > Signed-off-by: Radu Nicolau > --- > drivers/net/ixgbe/base/ixgbe_osdep.h | 6 ++++++ > drivers/net/ixgbe/ixgbe_rxtx.c | 12 ++++++------ > drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 4 ++-- > 3 files changed, 14 insertions(+), 8 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/bas= e/ixgbe_osdep.h > index dc712b7..cacf724 100644 > --- a/drivers/net/ixgbe/base/ixgbe_osdep.h > +++ b/drivers/net/ixgbe/base/ixgbe_osdep.h > @@ -105,6 +105,12 @@ static inline uint32_t ixgbe_read_addr(volatile void= * addr) > #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \ > rte_write32_relaxed((rte_cpu_to_le_32(value)), reg) >=20 > +#define IXGBE_PCI_REG_WC_WRITE(reg, value) \ > + rte_write32_wc((rte_cpu_to_le_32(value)), reg) > + > +#define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \ > + rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg) > + > #define IXGBE_PCI_REG_ADDR(hw, reg) \ > ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg))) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index 2e20e18..669b23e 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -308,7 +308,7 @@ tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkt= s, >=20 > /* update tail pointer */ > rte_wmb(); > - IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail); > + IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail); >=20 > return nb_pkts; > } > @@ -946,7 +946,7 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_= pkts, > PMD_TX_LOG(DEBUG, "port_id=3D%u queue_id=3D%u tx_tail=3D%u nb_tx=3D%u", > (unsigned) txq->port_id, (unsigned) txq->queue_id, > (unsigned) tx_id, (unsigned) nb_tx); > - IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id); > + IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id); > txq->tx_tail =3D tx_id; >=20 > return nb_tx; > @@ -1692,7 +1692,7 @@ rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_p= kts, >=20 > /* update tail pointer */ > rte_wmb(); > - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, > + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, > cur_free_trigger); > } >=20 > @@ -1918,7 +1918,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **r= x_pkts, > (unsigned) nb_rx); > rx_id =3D (uint16_t) ((rx_id =3D=3D 0) ? > (rxq->nb_rx_desc - 1) : (rx_id - 1)); > - IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id); > + IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id); > nb_hold =3D 0; > } > rxq->nb_rx_hold =3D nb_hold; > @@ -2096,7 +2096,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf= **rx_pkts, uint16_t nb_pkts, >=20 > if (!ixgbe_rx_alloc_bufs(rxq, false)) { > rte_wmb(); > - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, > + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, > next_rdt); > nb_hold -=3D rxq->rx_free_thresh; > } else { > @@ -2262,7 +2262,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf= **rx_pkts, uint16_t nb_pkts, > rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx); >=20 > rte_wmb(); > - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id); > + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id); > nb_hold =3D 0; > } >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/i= xgbe_rxtx_vec_sse.c > index 517ca31..e77a7f3 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c > @@ -90,7 +90,7 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq) > (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); >=20 > /* Update the tail pointer on the NIC */ > - IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id); > + IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id); > } >=20 > #ifdef RTE_LIBRTE_SECURITY > @@ -697,7 +697,7 @@ ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte= _mbuf **tx_pkts, >=20 > txq->tx_tail =3D tx_id; >=20 > - IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail); > + IXGBE_PCI_REG_WC_WRITE(txq->tdt_reg_addr, txq->tx_tail); >=20 > return nb_pkts; > } > -- Acked-by: Konstantin Ananyev > 2.7.4