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Thu, 8 Oct 2020 13:17:41 +0000 From: "Ananyev, Konstantin" To: "Power, Ciara" , "dev@dpdk.org" CC: Ruifeng Wang , Jerin Jacob , Honnappa Nagarahalli , David Christensen , Jan Viktorin , "Richardson, Bruce" Thread-Topic: [PATCH v3 02/18] eal: add default SIMD bitwidth values Thread-Index: AQHWlyrEyBXKGqfF6UiOzImy/ZKK3qmNurSw Date: Thu, 8 Oct 2020 13:17:41 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-3-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-3-ciara.power@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ec13565e-acc1-47a1-2a8e-08d86b8c8925 x-ms-traffictypediagnostic: BYAPR11MB2727: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ec13565e-acc1-47a1-2a8e-08d86b8c8925 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Oct 2020 13:17:41.1174 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mra7R47qV//2bkbpjAxnTiS5yfS/dhcBuhV0ulZaxTLS1zN9wZOsGVcnX3L0MrEaChEeQXnZlAyfmpAP+yZ85QG+5Ij7hRJ0IR/wfSOzx/8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2727 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 02/18] eal: add default SIMD bitwidth values X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Each arch has a define for the default SIMD bitwidth value, this is used > on EAL init to set the config max SIMD bitwidth. >=20 > Cc: Ruifeng Wang > Cc: Jerin Jacob > Cc: Honnappa Nagarahalli > Cc: David Christensen >=20 > Signed-off-by: Ciara Power >=20 > --- > v3: > - Removed unnecessary define in generic rte_vect.h > - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. > v2: Changed default bitwidth for Arm to 128. > --- > lib/librte_eal/arm/include/rte_vect.h | 2 ++ > lib/librte_eal/common/eal_common_options.c | 3 +++ > lib/librte_eal/ppc/include/rte_vect.h | 2 ++ > lib/librte_eal/x86/include/rte_vect.h | 2 ++ > 4 files changed, 9 insertions(+) >=20 > diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/i= nclude/rte_vect.h > index 01c51712a1..a3508e69d5 100644 > --- a/lib/librte_eal/arm/include/rte_vect.h > +++ b/lib/librte_eal/arm/include/rte_vect.h > @@ -14,6 +14,8 @@ > extern "C" { > #endif >=20 > +#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX As a nit - can we use here values from enum rte_max_simd_t? That would make things more consistent... Probably you'll need to move enum rte_max_simd_t definition into rte_vect.h for that. > + > typedef int32x4_t xmm_t; >=20 > #define XMM_SIZE (sizeof(xmm_t)) > diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/= common/eal_common_options.c > index e9117a96af..d412cae89b 100644 > --- a/lib/librte_eal/common/eal_common_options.c > +++ b/lib/librte_eal/common/eal_common_options.c > @@ -35,6 +35,7 @@ > #ifndef RTE_EXEC_ENV_WINDOWS > #include > #endif > +#include >=20 > #include "eal_internal_cfg.h" > #include "eal_options.h" > @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *int= ernal_cfg) > internal_cfg->user_mbuf_pool_ops_name =3D NULL; > CPU_ZERO(&internal_cfg->ctrl_cpuset); > internal_cfg->init_complete =3D 0; > + internal_cfg->max_simd_bitwidth.bitwidth =3D RTE_DEFAULT_SIMD_BITWIDTH; > + internal_cfg->max_simd_bitwidth.locked =3D 0; > } >=20 > static int > diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/i= nclude/rte_vect.h > index b0545c878c..70fbd0c423 100644 > --- a/lib/librte_eal/ppc/include/rte_vect.h > +++ b/lib/librte_eal/ppc/include/rte_vect.h > @@ -15,6 +15,8 @@ > extern "C" { > #endif >=20 > +#define RTE_DEFAULT_SIMD_BITWIDTH 256 > + > typedef vector signed int xmm_t; >=20 > #define XMM_SIZE (sizeof(xmm_t)) > diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/i= nclude/rte_vect.h > index df5a607623..b1df75aca7 100644 > --- a/lib/librte_eal/x86/include/rte_vect.h > +++ b/lib/librte_eal/x86/include/rte_vect.h > @@ -35,6 +35,8 @@ > extern "C" { > #endif >=20 > +#define RTE_DEFAULT_SIMD_BITWIDTH 256 > + > typedef __m128i xmm_t; >=20 > #define XMM_SIZE (sizeof(xmm_t)) > -- > 2.17.1