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Wed, 8 Jul 2020 12:23:12 +0000 Received: from BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f160:29ab:b8f9:4189]) by BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f160:29ab:b8f9:4189%6]) with mapi id 15.20.3153.031; Wed, 8 Jul 2020 12:23:12 +0000 From: "Ananyev, Konstantin" To: "Medvedkin, Vladimir" , "dev@dpdk.org" CC: "Richardson, Bruce" Thread-Topic: [PATCH v3 7/8] fib6: introduce AVX512 lookup Thread-Index: AQHWLdb0A2IzRxPZNE+wfI/8PpgWY6j96HGw Date: Wed, 8 Jul 2020 12:23:12 +0000 Message-ID: References: <99bcffd72d5678e58289830c43ce2bf3829d310a.1589890263.git.vladimir.medvedkin@intel.com> In-Reply-To: <99bcffd72d5678e58289830c43ce2bf3829d310a.1589890263.git.vladimir.medvedkin@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 7c1LAuUAy2jQVJQ99B5CotpRV3JUbmNAL6Hv/WsMCt46dTPNngIaGFutsngWAwiBnPsJPhl3LvanHC3iMA+RrV3PyaWbR2VvSB1mKb8pwnxKG3hUYEezvI2qGpxy1LQl1M1t5Obs9FCNz20+pdZLnyLd5IoRgWbxREqGbn1HIVbG72jGBAojZjAbW3BbftaoJHveOuiIESvTm2r+brfvshFI35KCXNjF2/tQ+yQAkFzjpShy6LkYMbGws/TX0FJhZFtaYHntqxKERZJdRZF5mS0n0TmOLdLwn9g3FXREKBA0t/+tZMDrhFbNV2ZQB+FHWjZpYTfDn2FX5nC2dcHmcQSDDhV4NJm6P2eRAo6/QzA1e5DJeLXwJ932U4ZugnjuGP2fRbnKSPOIaC2wygC7mnrObNmwa/Ny3N5mrJDHCzYS2vU2pr9ZWSfWs+vs2MMbFZAWzDjjmIjD4VwEP6c0nOJaghtF3BHOTIj1whRe2dUUydvR0Eqc97WtRHybH3H/ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f6d82660-7a16-4850-0e6e-08d82339aee6 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jul 2020 12:23:12.5506 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hr9LptPSHC7g2vNtFEiPYAzBxzxsC+edH1KuA+WZfbKauguab1b9OZtog64aw4pOtoGjGfW0pPIsK05v625X8KTNXQcltAkMUoIMNThl+ZY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4006 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 7/8] fib6: introduce AVX512 lookup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: >=20 > Add new lookup implementation for FIB6 trie algorithm using > AVX512 instruction set >=20 > Signed-off-by: Vladimir Medvedkin > --- > lib/librte_fib/Makefile | 10 ++ > lib/librte_fib/meson.build | 9 ++ > lib/librte_fib/rte_fib6.h | 3 +- > lib/librte_fib/trie.c | 21 ++++ > lib/librte_fib/trie_avx512.c | 269 +++++++++++++++++++++++++++++++++++++= ++++++ > lib/librte_fib/trie_avx512.h | 20 ++++ > 6 files changed, 331 insertions(+), 1 deletion(-) > create mode 100644 lib/librte_fib/trie_avx512.c > create mode 100644 lib/librte_fib/trie_avx512.h >=20 > diff --git a/lib/librte_fib/Makefile b/lib/librte_fib/Makefile > index 3958da1..761c7c8 100644 > --- a/lib/librte_fib/Makefile > +++ b/lib/librte_fib/Makefile > @@ -25,12 +25,22 @@ grep -q __AVX512F__ && echo 1) > CC_AVX512DQ_SUPPORT=3D$(shell $(CC) -mavx512dq -dM -E - &1 = | \ > grep -q __AVX512DQ__ && echo 1) >=20 > +CC_AVX512BW_SUPPORT=3D$(shell $(CC) -mavx512bw -dM -E - &1 = | \ > +grep -q __AVX512BW__ && echo 1) > + > ifeq ($(CC_AVX512F_SUPPORT), 1) > ifeq ($(CC_AVX512DQ_SUPPORT), 1) > SRCS-$(CONFIG_RTE_LIBRTE_FIB) +=3D dir24_8_avx512.c > CFLAGS_dir24_8_avx512.o +=3D -mavx512f > CFLAGS_dir24_8_avx512.o +=3D -mavx512dq > CFLAGS_dir24_8.o +=3D -DCC_DIR24_8_AVX512_SUPPORT > + ifeq ($(CC_AVX512BW_SUPPORT), 1) > + SRCS-$(CONFIG_RTE_LIBRTE_FIB) +=3D trie_avx512.c > + CFLAGS_trie_avx512.o +=3D -mavx512f > + CFLAGS_trie_avx512.o +=3D -mavx512dq > + CFLAGS_trie_avx512.o +=3D -mavx512bw > + CFLAGS_trie.o +=3D -DCC_TRIE_AVX512_SUPPORT > + endif > endif > endif > include $(RTE_SDK)/mk/rte.lib.mk > diff --git a/lib/librte_fib/meson.build b/lib/librte_fib/meson.build > index 0963f3c..98adf11 100644 > --- a/lib/librte_fib/meson.build > +++ b/lib/librte_fib/meson.build > @@ -14,5 +14,14 @@ if dpdk_conf.has('RTE_ARCH_X86') and cc.has_argument('= -mavx512f') > c_args: cflags + ['-mavx512f'] + ['-mavx512dq']) > objs +=3D dir24_8_avx512_tmp.extract_objects('dir24_8_avx512.c') > cflags +=3D '-DCC_DIR24_8_AVX512_SUPPORT' > + if cc.has_argument('-mavx512bw') > + trie_avx512_tmp =3D static_library('trie_avx512_tmp', > + 'trie_avx512.c', > + dependencies: static_rte_eal, > + c_args: cflags + ['-mavx512f'] + \ > + ['-mavx512dq'] + ['-mavx512bw']) > + objs +=3D trie_avx512_tmp.extract_objects('trie_avx512.c') > + cflags +=3D '-DCC_TRIE_AVX512_SUPPORT' > + endif > endif > endif > diff --git a/lib/librte_fib/rte_fib6.h b/lib/librte_fib/rte_fib6.h > index b70369a..c55efdf 100644 > --- a/lib/librte_fib/rte_fib6.h > +++ b/lib/librte_fib/rte_fib6.h > @@ -53,7 +53,8 @@ enum rte_fib_trie_nh_sz { > }; >=20 > enum rte_fib_trie_lookup_type { > - RTE_FIB6_TRIE_SCALAR > + RTE_FIB6_TRIE_SCALAR, > + RTE_FIB6_TRIE_VECTOR As a nit - does this enum needs to be public? If it does, then probably worth to name it VECTOR_AVX512, in case someone in future will want to add another vector implementation. Probably same thought for v4. Apart from that - LGTM. Acked-by: Konstantin Ananyev =20