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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3352.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b71492c2-762b-451a-35d6-08d8655871e0 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2020 15:49:41.1803 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kTyBBb5HGVrw2AcYelwINrn9eWvwVMQhhOkXtKdosy09SUXqJK6KEZsZyA2ASpxci1suKvqskYtrYH0dN+x35bBP8zfR5o9ybL/xxAZCG4Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2678 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Coyle, David > Sent: Wednesday, September 30, 2020 4:04 PM > To: Power, Ciara ; dev@dpdk.org > Cc: Power, Ciara ; Singh, Jasvinder > ; Olivier Matz ; > O'loingsigh, Mairtin ; Ryan, Brendan > ; Richardson, Bruce > > Subject: RE: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD > bitwidth >=20 > Hi Ciara, >=20 > > From: dev On Behalf Of Ciara Power When > > choosing a vector path to take, an extra condition must be satisfied > > to ensure the max SIMD bitwidth allows for the CPU enabled path. > > > > The vector path was initially chosen in RTE_INIT, however this is no > > longer suitable as we cannot check the max SIMD bitwidth at that time. > > The default chosen in RTE_INIT is now scalar. For best performance and > > to use vector paths, apps must explicitly call the set algorithm > > function before using other functions from this library, as this is > > where vector handlers are now chosen. >=20 > [DC] Has it been decided that it is ok to now require applications to pic= k the > CRC algorithm they want to use? >=20 > An application which previously automatically got SSE4.2 CRC, for example= , > will now automatically only get scalar. >=20 > If this is ok, this should probably be called out explicitly in release n= otes as it > may not be Immediately noticeable to users that they now need to select t= he > CRC algo. >=20 > Actually, in general, the release notes need to be updated for this patch= set. The decision to move rte_set_alg() out of RTE_INIT was taken to avoid check= on max_simd_bitwidth in data path for every single time when crc_calc() ap= i is invoked. Based on my understanding, max_simd_bitwidth is set after eal= init, and when used in crc_calc(), it might override the default crc algo = set during RTE_INIT. Therefore, to avoid extra check on max_simd_bitwidth i= n data path, better option will be to use this static configuration one ti= me after eal init in the set_algo API.=20 =20 > > > > Suggested-by: Jasvinder Singh > > > > Signed-off-by: Ciara Power > > > > --- > > v3: > > - Moved choosing vector paths out of RTE_INIT. > > - Moved checking max_simd_bitwidth into the set_alg function. > > --- > > lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++--------- > > lib/librte_net/rte_net_crc.h | 3 ++- > > 2 files changed, 19 insertions(+), 10 deletions(-) > > > > diff --git a/lib/librte_net/rte_net_crc.c > > b/lib/librte_net/rte_net_crc.c index > > 9fd4794a9d..241eb16399 100644 > > --- a/lib/librte_net/rte_net_crc.c > > +++ b/lib/librte_net/rte_net_crc.c >=20 > >=20 > > @@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data, > > uint32_t data_len) void rte_net_crc_set_alg(enum rte_net_crc_alg > > alg) { > > + if (max_simd_bitwidth =3D=3D 0) > > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > > + > > switch (alg) { > > #ifdef X86_64_SSE42_PCLMULQDQ > > case RTE_NET_CRC_SSE42: > > - handlers =3D handlers_sse42; > > - break; > > + if (max_simd_bitwidth >=3D RTE_MAX_128_SIMD) { > > + handlers =3D handlers_sse42; > > + return; > > + } > > + RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low, using > > scalar\n"); >=20 > [DC] Not sure if you're aware but there is another patchset which adds an > AVX512 CRC implementation and run-time checking of cpuflags to select the > CRC path to use: > https://patchwork.dpdk.org/project/dpdk/list/?series=3D12596 >=20 > There will be a task to merge these 2 patchsets if both are merged. It lo= oks > fairly straightforward to me to merge these, but it would be good if you = take > a look too