From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
	by inbox.dpdk.org (Postfix) with ESMTP id 73148A04B5;
	Wed, 30 Sep 2020 17:49:57 +0200 (CEST)
Received: from [92.243.14.124] (localhost [127.0.0.1])
	by dpdk.org (Postfix) with ESMTP id 89E5E1D447;
	Wed, 30 Sep 2020 17:49:54 +0200 (CEST)
Received: from mga02.intel.com (mga02.intel.com [134.134.136.20])
 by dpdk.org (Postfix) with ESMTP id C99F01C29D
 for <dev@dpdk.org>; Wed, 30 Sep 2020 17:49:51 +0200 (CEST)
IronPort-SDR: P+HPNBu4P5ke/q5rYW/bL+mg0+JgaC15RL/UiGvVjja3mp3sw4DWjByTXYCkKedCPOJqJ7exL/
 75GbhMaqLrPQ==
X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150137054"
X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150137054"
X-Amp-Result: SKIPPED(no attachment in message)
X-Amp-File-Uploaded: False
Received: from fmsmga005.fm.intel.com ([10.253.24.32])
 by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
 30 Sep 2020 08:49:49 -0700
IronPort-SDR: HA9OkvjRcwH/jhoi3FhulMVR24Wr3ZnXVR85cHA4iOjr7AAJmUv7tMscMa1uesf1tuJTOYVTqc
 B2CSvkc6SZrg==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="515123630"
Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16])
 by fmsmga005.fm.intel.com with ESMTP; 30 Sep 2020 08:49:49 -0700
Received: from orsmsx607.amr.corp.intel.com (10.22.229.20) by
 ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.1713.5; Wed, 30 Sep 2020 08:49:48 -0700
Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by
 orsmsx607.amr.corp.intel.com (10.22.229.20) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5
 via Frontend Transport; Wed, 30 Sep 2020 08:49:48 -0700
Received: from NAM10-BN7-obe.outbound.protection.outlook.com (104.47.70.102)
 by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
 15.1.1713.5; Wed, 30 Sep 2020 08:49:48 -0700
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
 b=SkChiqV3B0gGDfnbr8JhD0F/FeyTWLfnMlCbbETSqj9dWD0nz2eRQt25UYkiuzfyTNqtZStKCqIUCbxcV4arkVsOmLq+FddJpvf5xZ1HKbdkEtaUorSMFCTsx3vS643ng3nWs58wzM+P8C0qhdYR2ipQxS+wl/UoAkK+XGKKDk2M24PyjfJ+O0geGgySkMEHaaF2PmTZ6SJlPxA7Bkuibe/J3Ug0UdGR5xlpgb6bwEIAeUIfHcnkKvBd4F4wLdn+JopL2zrDbt/XKfLjK9KwthwPZP809kggXkVaA+G3f0Z3B8fo/sCMpegMpts+prEuLl5zE8pPBudoCdTV1rwWgg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; 
 s=arcselector9901;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=KbovM3y6cB9IR9cpv7q7CLKxH3IWVrlvI71Dska5G30=;
 b=WPNOyOp9zmAvAJYtkTlQb+tbtBmGUDMPrtEPij+Vw+NH6HQ5qmqh9RdsqkhfTLpubJ3DUb9BTP6qj2X3HsUiungFk/Z9/aaunSg414FPgdJpW4Ic24YL66JqQMjSXGE2xRv4fuI2WXvcwkWKSjjeooXe2B6HA7wzDrzCY+8umxAdzqCR0sVpVJJa2NB8aaJq7q9wo7RDcFuLhZKfyTtW3YDclF4ix8TafRIdyw4fA2io7mvt+Cv7dMG+olkgMJpEG85JJI6Z386chscmzthMTZ/L7e+q3AVHdLPz/6hX6kGG8TTLn2wlPWlecV6wqPeeRSNmz+ZRxIrCX9mtSK9VDg==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass
 smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;
 dkim=pass header.d=intel.com; arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; 
 s=selector2-intel-onmicrosoft-com;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=KbovM3y6cB9IR9cpv7q7CLKxH3IWVrlvI71Dska5G30=;
 b=jI9ROEuMU0mYNSg1Jjf93EQpqkSu8QouqDfEk+cuja9W7WWIVnaqqd42Ljb/6aae2WFmF66+t5eJElq47YpNFc5tjU2OJgxXomvIcAghfvEHerCXYIL8oX/ENfZJfBERQKXldW/PhSlnSKBEw5XRnU0z/ESzCXsHTmiQBZkN6z0=
Received: from BYAPR11MB3352.namprd11.prod.outlook.com (2603:10b6:a03:1d::26)
 by BYAPR11MB2678.namprd11.prod.outlook.com (2603:10b6:a02:c1::22)
 with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3412.20; Wed, 30 Sep
 2020 15:49:41 +0000
Received: from BYAPR11MB3352.namprd11.prod.outlook.com
 ([fe80::9d60:ddf8:226:8eb6]) by BYAPR11MB3352.namprd11.prod.outlook.com
 ([fe80::9d60:ddf8:226:8eb6%7]) with mapi id 15.20.3412.029; Wed, 30 Sep 2020
 15:49:41 +0000
From: "Singh, Jasvinder" <jasvinder.singh@intel.com>
To: "Coyle, David" <david.coyle@intel.com>, "Power, Ciara"
 <ciara.power@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
CC: "Power, Ciara" <ciara.power@intel.com>, Olivier Matz
 <olivier.matz@6wind.com>, "O'loingsigh, Mairtin"
 <mairtin.oloingsigh@intel.com>, "Ryan, Brendan" <brendan.ryan@intel.com>,
 "Richardson, Bruce" <bruce.richardson@intel.com>
Thread-Topic: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD bitwidth
Thread-Index: AQHWlyrPO1m3IIRP60qn8RAuGWMQhamBR3WAgAAJq2A=
Date: Wed, 30 Sep 2020 15:49:41 +0000
Message-ID: <BYAPR11MB3352BF18F80E88072A4D5BC9E0330@BYAPR11MB3352.namprd11.prod.outlook.com>
References: <20200807155859.63888-1-ciara.power@intel.com>
 <20200930130415.11211-1-ciara.power@intel.com>
 <20200930130415.11211-18-ciara.power@intel.com>
 <MN2PR11MB35500150FE7C85DD6BF352C2E3330@MN2PR11MB3550.namprd11.prod.outlook.com>
In-Reply-To: <MN2PR11MB35500150FE7C85DD6BF352C2E3330@MN2PR11MB3550.namprd11.prod.outlook.com>
Accept-Language: en-GB, en-US
Content-Language: en-US
X-MS-Has-Attach: 
X-MS-TNEF-Correlator: 
dlp-version: 11.5.1.3
dlp-reaction: no-action
dlp-product: dlpe-windows
authentication-results: intel.com; dkim=none (message not signed)
 header.d=none;intel.com; dmarc=none action=none header.from=intel.com;
x-originating-ip: [51.37.138.153]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: b71492c2-762b-451a-35d6-08d8655871e0
x-ms-traffictypediagnostic: BYAPR11MB2678:
x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr
x-ms-exchange-transport-forked: True
x-microsoft-antispam-prvs: <BYAPR11MB2678848789A2461B221C269EE0330@BYAPR11MB2678.namprd11.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:10000;
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: YgdyWpu51BMGTM/USAiBN3NgcKRVmDnC5d818uockqlGc5dTlW7TRh6WDBxSnVDgQPuUgMqM7Gig6KI7+fkvydHGnQWp4hO0l/VonsLntdUhnxHm9CZkFpqTeO78AgwiIfPsAlD5qpYxofIzSsPjkOH44kwV78eo2s30/AFYn1KkTPb5nNiREY8UxJ1llIxZb4u5LOHxFsWZbzIGbU/Ar8+UWRiniKBArchkn/cNvnADDvoh4NrRWNnm28d65gRzQSJXnmLZW36wfPIxwla71+DbfPX0Z5IqOibyoe+7gIuj4pZx+oQlFiN43J9W7PByzqehYlfM+gXtgLe1HCgsGqfz6EqYXq6KqAR5QhKC8Q075aCIxZqU52y+EJ69iTMKoWQ73mCDv26UZ8BgHVPkF+s74SipH1ISZbadeblKG7eOVcoJhWoknljWoFNR65E0uJh05PBavxvlxRW6fiWrOg==
x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;
 IPV:NLI; SFV:NSPM; H:BYAPR11MB3352.namprd11.prod.outlook.com; PTR:; CAT:NONE;
 SFS:(4636009)(396003)(136003)(39860400002)(346002)(376002)(366004)(7696005)(55016002)(66946007)(6506007)(76116006)(8936002)(478600001)(66446008)(26005)(64756008)(33656002)(66476007)(83380400001)(107886003)(53546011)(9686003)(66556008)(966005)(186003)(71200400001)(86362001)(5660300002)(8676002)(52536014)(2906002)(4326008)(110136005)(54906003)(316002);
 DIR:OUT; SFP:1102; 
x-ms-exchange-antispam-messagedata: /+Ab1ugfNrbTmJk5mvlUCzfzhrAlHYdesxmr0DFIypl+AiMvKmDTlOgkFQMyAHzB6OYAbDIKF2bcH5cCMUtG4mASLyyStqb0fpp7bbA7t0ubSl9ygbn6kkZ3l6qEk7MgN72/00TJq10n+Oy/4evvAjPxo3lWGl3diIfw1f8LmdXJi1xlfHbIeCdoE7O0SBz931uia/+L5dOEyG/xVKjUAXY1NrQlKJhvBBMHMdKMM3C/uxXGpPoTlDhOMnugQOo0JG1nLRsQijjJdhhWupiYno+WRmlQabCeBMsDHa7bI1if//VKd/KTWOoMk8MJVmlVKRNeY6EjA98W4pt73RqO5Eh20nnFHzIK3OfNz5b16bwlLiYZIOJw69vuYKHHE2Plu+m4aQgk8o8xtbK3G7hr7dqh5SIDcZzOWTGgOzKjdqXWoh+RS0d83e62bdWW80Jb2+0YDjbvS56H58hyEkmw6XsOfuYwSFP8N3BRJgngGF30TvLRfe9DR9rhwrknd+GWXYjA0JpSv65JtqeX1TQfjtkMpUMFbWncpDKeIfE9faVSV8Cm9mQOtVeukjo3diHu/0kxXUX2oy1ap89X07hXvx1CsUfIcQbqB06wY0wW2SPIotoN6OLaIHXc4xn3DT7jbv/bipuSvIpc9SHHjoXlzg==
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3352.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: b71492c2-762b-451a-35d6-08d8655871e0
X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2020 15:49:41.1803 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: kTyBBb5HGVrw2AcYelwINrn9eWvwVMQhhOkXtKdosy09SUXqJK6KEZsZyA2ASpxci1suKvqskYtrYH0dN+x35bBP8zfR5o9ybL/xxAZCG4Q=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2678
X-OriginatorOrg: intel.com
Subject: Re: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD
	bitwidth
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>



> -----Original Message-----
> From: Coyle, David <david.coyle@intel.com>
> Sent: Wednesday, September 30, 2020 4:04 PM
> To: Power, Ciara <ciara.power@intel.com>; dev@dpdk.org
> Cc: Power, Ciara <ciara.power@intel.com>; Singh, Jasvinder
> <jasvinder.singh@intel.com>; Olivier Matz <olivier.matz@6wind.com>;
> O'loingsigh, Mairtin <mairtin.oloingsigh@intel.com>; Ryan, Brendan
> <brendan.ryan@intel.com>; Richardson, Bruce
> <bruce.richardson@intel.com>
> Subject: RE: [dpdk-dev] [PATCH v3 17/18] net: add checks for max SIMD
> bitwidth
>=20
> Hi Ciara,
>=20
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Ciara Power When
> > choosing a vector path to take, an extra condition must be satisfied
> > to ensure the max SIMD bitwidth allows for the CPU enabled path.
> >
> > The vector path was initially chosen in RTE_INIT, however this is no
> > longer suitable as we cannot check the max SIMD bitwidth at that time.
> > The default chosen in RTE_INIT is now scalar. For best performance and
> > to use vector paths, apps must explicitly call the set algorithm
> > function before using other functions from this library, as this is
> > where vector handlers are now chosen.
>=20
> [DC] Has it been decided that it is ok to now require applications to pic=
k the
> CRC algorithm they want to use?
>=20
> An application which previously automatically got SSE4.2 CRC, for example=
,
> will now automatically only get scalar.
>=20
> If this is ok, this should probably be called out explicitly in release n=
otes as it
> may not be Immediately noticeable to users that they now need to select t=
he
> CRC algo.
>=20
> Actually, in general, the release notes need to be updated for this patch=
set.

The decision to move rte_set_alg() out of RTE_INIT was taken to avoid check=
 on max_simd_bitwidth in data path for every single time when crc_calc() ap=
i is invoked. Based on my understanding, max_simd_bitwidth is set after eal=
 init, and when used in crc_calc(), it might override the default crc algo =
set during RTE_INIT. Therefore, to avoid extra check on max_simd_bitwidth i=
n data path,  better option will be to use this static configuration one ti=
me after eal init in the set_algo API.=20

=20
> >
> > Suggested-by: Jasvinder Singh <jasvinder.singh@intel.com>
> >
> > Signed-off-by: Ciara Power <ciara.power@intel.com>
> >
> > ---
> > v3:
> >   - Moved choosing vector paths out of RTE_INIT.
> >   - Moved checking max_simd_bitwidth into the set_alg function.
> > ---
> >  lib/librte_net/rte_net_crc.c | 26 +++++++++++++++++---------
> > lib/librte_net/rte_net_crc.h |  3 ++-
> >  2 files changed, 19 insertions(+), 10 deletions(-)
> >
> > diff --git a/lib/librte_net/rte_net_crc.c
> > b/lib/librte_net/rte_net_crc.c index
> > 9fd4794a9d..241eb16399 100644
> > --- a/lib/librte_net/rte_net_crc.c
> > +++ b/lib/librte_net/rte_net_crc.c
>=20
> <snip>
>=20
> > @@ -145,18 +149,26 @@ rte_crc32_eth_handler(const uint8_t *data,
> > uint32_t data_len)  void  rte_net_crc_set_alg(enum rte_net_crc_alg
> > alg)  {
> > +	if (max_simd_bitwidth =3D=3D 0)
> > +		max_simd_bitwidth =3D rte_get_max_simd_bitwidth();
> > +
> >  	switch (alg) {
> >  #ifdef X86_64_SSE42_PCLMULQDQ
> >  	case RTE_NET_CRC_SSE42:
> > -		handlers =3D handlers_sse42;
> > -		break;
> > +		if (max_simd_bitwidth >=3D RTE_MAX_128_SIMD) {
> > +			handlers =3D handlers_sse42;
> > +			return;
> > +		}
> > +		RTE_LOG(INFO, NET, "Max SIMD Bitwidth too low, using
> > scalar\n");
>=20
> [DC] Not sure if you're aware but there is another patchset which adds an
> AVX512 CRC implementation and run-time checking of cpuflags to select the
> CRC path to use:
> https://patchwork.dpdk.org/project/dpdk/list/?series=3D12596
>=20
> There will be a task to merge these 2 patchsets if both are merged. It lo=
oks
> fairly straightforward to me to merge these, but it would be good if you =
take
> a look too