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Fri, 2 Oct 2020 15:17:46 +0000 From: "Singh, Jasvinder" To: "O'loingsigh, Mairtin" , "Richardson, Bruce" , "De Lara Guarch, Pablo" CC: "dev@dpdk.org" , "Ryan, Brendan" , "Coyle, David" Thread-Topic: [PATCH v3 1/2] net: add run-time architecture specific CRC selection Thread-Index: AQHWlnZK+fUON5vP2ESTCJbjzcATVqmEcCtw Date: Fri, 2 Oct 2020 15:17:46 +0000 Message-ID: References: <1601393761-11588-1-git-send-email-mairtin.oloingsigh@intel.com> <1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com> In-Reply-To: <1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [51.37.138.153] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 47a3e964-5d77-4575-c58e-08d866e65165 x-ms-traffictypediagnostic: BY5PR11MB4242: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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SFP:1102; x-ms-exchange-antispam-messagedata: wMMEpOX8xJnsBkXCwnExhY5FwRjdOxLYtnA3j9y2VHAmC9uM21L0GdVdBKM2g/I6h9QKHX6vpyQO7VkP1n4PIx3SOh1enFCpSu76doALSamCAQvecmim46KAxWDNbsLYLNfUrdkn/HmHaDSPsy+eV2M1HJwmhBZR9+8lOkAkUzSpwGugZnE2vHET1Fy96ip9RUW+4fAO/h9xGB9PRjjf3uAnP6O32iWruWU7sg7iZeRp19Y+6kBKOhgfMHvf2MILO2mCeu+nUdxz+rcuIfxxsa3YISiAWq/wvT1sz+PhVLInC4OJr3DbI/lBe3ZzRTx7JEQRCXutcitqLK7tCQWDNgRPCEgyX/1eNRe+tfMlSrEqeFdNNv67dyfvK7cz+6/W1vk5m6CV7wJAAlfqQoHtKXVAshzcLWEBdkGdwFv3pAZ72HMvEnA5LT/SxFtXB8mNRVYHrysI3BckG57+dRm5aaJtriwUui0oJM2epLXi5a0rrYkwYhcOi5CF6OX0ZyLxgF6x/eBlExFzUn+tIxhgD3ntCfvSE7XmOtAHC1E9+mQxrLjFqSWklwWbqKVT759KXW8HxYYxEHxurUXhxY8h7xZRAT5a16D+Js4y2QiIsC1ihYYatT7i2htcyzLLEShRRVcZGyvnBPSTF3Z9990Wmg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3352.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 47a3e964-5d77-4575-c58e-08d866e65165 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Oct 2020 15:17:46.4482 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ut7kaPIYRqigDEujSieqoETlAzCWUqek8gkKCbxxkQ06qUoWvpgYt5oQ9Wi/Iw6EyTe+VUK1ByTEGyyePo2ScQx4XXcEsF8PCCuz3WejYTQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4242 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 1/2] net: add run-time architecture specific CRC selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: O'loingsigh, Mairtin > Sent: Tuesday, September 29, 2020 4:36 PM > To: Singh, Jasvinder ; Richardson, Bruce > ; De Lara Guarch, Pablo > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, David > ; O'loingsigh, Mairtin > > Subject: [PATCH v3 1/2] net: add run-time architecture specific CRC selec= tion >=20 > This patch adds support for run-time selection of the optimal architectur= e- > specific CRC path, based on the supported instruction set(s) of the CPU. >=20 > The compiler option checks have been moved from the C files to the meson > script. The rte_cpu_get_flag_enabled function is called automatically by = the > library at process initialization time to determine which instructions th= e CPU > supports, with the most optimal supported CRC path ultimately selected. >=20 > Signed-off-by: Mairtin o Loingsigh > Signed-off-by: David Coyle > --- > doc/guides/rel_notes/release_20_11.rst | 4 ++ > lib/librte_net/meson.build | 34 +++++++++++- > lib/librte_net/net_crc.h | 34 ++++++++++++ > lib/librte_net/{net_crc_neon.h =3D> net_crc_neon.c} | 27 +++------ > lib/librte_net/{net_crc_sse.h =3D> net_crc_sse.c} | 34 ++++-------- > lib/librte_net/rte_net_crc.c | 67 ++++++++++++++---= ------ > 6 files changed, 132 insertions(+), 68 deletions(-) create mode 100644 > lib/librte_net/net_crc.h rename lib/librte_net/{net_crc_neon.h =3D> > net_crc_neon.c} (95%) rename lib/librte_net/{net_crc_sse.h =3D> > net_crc_sse.c} (94%) >=20 > diff --git a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index 4eb3224a7..6bd222dca 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -55,6 +55,10 @@ New Features > Also, make sure to start the actual text at the margin. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D _t *data, uint32_t data_len); > + > +#endif /* _NET_CRC_H_ */ > diff --git a/lib/librte_net/net_crc_neon.h b/lib/librte_net/net_crc_neon.= c > similarity index 95% rename from lib/librte_net/net_crc_neon.h rename to > lib/librte_net/net_crc_neon.c index 63fa1d4a1..b79684ec2 100644 > --- a/lib/librte_net/net_crc_neon.h > +++ b/lib/librte_net/net_crc_neon.c > @@ -1,18 +1,17 @@ > /* SPDX-License-Identifier: BSD-3-Clause > * Copyright(c) 2017 Cavium, Inc > + * Copyright(c) 2020 Intel Corporation > */ Could you please remove intel copyright as there is no change in this file?= =20 > -#ifndef _NET_CRC_NEON_H_ > -#define _NET_CRC_NEON_H_ > +#include >=20 > +#include > #include > #include > #include > #include >=20 > -#ifdef __cplusplus > -extern "C" { > -#endif > +#include "net_crc.h" >=20 > /** PMULL CRC computation context structure */ struct crc_pmull_ctx { @= @ > -218,7 +217,7 @@ crc32_eth_calc_pmull( > return n; > } >=20 > -static inline void > +void > rte_net_crc_neon_init(void) > { > /* Initialize CRC16 data */ > @@ -242,9 +241,8 @@ rte_net_crc_neon_init(void) > crc32_eth_pmull.rk7_rk8 =3D vld1q_u64(eth_k7_k8); } >=20 > -static inline uint32_t > -rte_crc16_ccitt_neon_handler(const uint8_t *data, > - uint32_t data_len) > +uint32_t > +rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len) > { > return (uint16_t)~crc32_eth_calc_pmull(data, > data_len, > @@ -252,18 +250,11 @@ rte_crc16_ccitt_neon_handler(const uint8_t *data, > &crc16_ccitt_pmull); > } >=20 > -static inline uint32_t > -rte_crc32_eth_neon_handler(const uint8_t *data, > - uint32_t data_len) > +uint32_t > +rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len) > { > return ~crc32_eth_calc_pmull(data, > data_len, > 0xffffffffUL, > &crc32_eth_pmull); > } > - > -#ifdef __cplusplus > -} > -#endif > - > -#endif /* _NET_CRC_NEON_H_ */ > diff --git a/lib/librte_net/net_crc_sse.h b/lib/librte_net/net_crc_sse.c > similarity index 94% rename from lib/librte_net/net_crc_sse.h rename to > lib/librte_net/net_crc_sse.c index 1c7b7a548..053b54b39 100644 > --- a/lib/librte_net/net_crc_sse.h > +++ b/lib/librte_net/net_crc_sse.c > @@ -1,18 +1,16 @@ > /* SPDX-License-Identifier: BSD-3-Clause > - * Copyright(c) 2017 Intel Corporation > + * Copyright(c) 2017-2020 Intel Corporation > */ >=20 > -#ifndef _RTE_NET_CRC_SSE_H_ > -#define _RTE_NET_CRC_SSE_H_ > +#include >=20 > +#include > #include > +#include >=20 > -#include > -#include > +#include "net_crc.h" >=20 > -#ifdef __cplusplus > -extern "C" { > -#endif > +#include >=20 > /** PCLMULQDQ CRC computation context structure */ struct > crc_pclmulqdq_ctx { @@ -259,8 +257,7 @@ crc32_eth_calc_pclmulqdq( > return n; > } >=20 > - > -static inline void > +void > rte_net_crc_sse42_init(void) > { > uint64_t k1, k2, k5, k6; > @@ -303,12 +300,10 @@ rte_net_crc_sse42_init(void) > * use other data types such as float, double, etc. > */ > _mm_empty(); > - > } >=20 > -static inline uint32_t > -rte_crc16_ccitt_sse42_handler(const uint8_t *data, > - uint32_t data_len) > +uint32_t > +rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len) > { > /** return 16-bit CRC value */ > return (uint16_t)~crc32_eth_calc_pclmulqdq(data, > @@ -317,18 +312,11 @@ rte_crc16_ccitt_sse42_handler(const uint8_t > *data, > &crc16_ccitt_pclmulqdq); > } >=20 > -static inline uint32_t > -rte_crc32_eth_sse42_handler(const uint8_t *data, > - uint32_t data_len) > +uint32_t > +rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len) > { > return ~crc32_eth_calc_pclmulqdq(data, > data_len, > 0xffffffffUL, > &crc32_eth_pclmulqdq); > } > - > -#ifdef __cplusplus > -} > -#endif > - > -#endif /* _RTE_NET_CRC_SSE_H_ */ > diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c = index > 4f5b9e828..83dccbfba 100644 > --- a/lib/librte_net/rte_net_crc.c > +++ b/lib/librte_net/rte_net_crc.c > @@ -1,5 +1,5 @@ > /* SPDX-License-Identifier: BSD-3-Clause > - * Copyright(c) 2017 Intel Corporation > + * Copyright(c) 2017-2020 Intel Corporation > */ >=20 > #include > @@ -10,17 +10,7 @@ > #include > #include >=20 > -#if defined(RTE_ARCH_X86_64) && defined(__PCLMUL__) > -#define X86_64_SSE42_PCLMULQDQ 1 > -#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRYPTO) > -#define ARM64_NEON_PMULL 1 > -#endif > - > -#ifdef X86_64_SSE42_PCLMULQDQ > -#include > -#elif defined ARM64_NEON_PMULL > -#include > -#endif > +#include "net_crc.h" >=20 > /** CRC polynomials */ > #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL @@ -47,13 +37,13 @@ > static rte_net_crc_handler handlers_scalar[] =3D { > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_handler, > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_handler, }; > - > -#ifdef X86_64_SSE42_PCLMULQDQ > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > static rte_net_crc_handler handlers_sse42[] =3D { > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_sse42_handler, > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_sse42_handler, }; -#elif > defined ARM64_NEON_PMULL > +#endif > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > static rte_net_crc_handler handlers_neon[] =3D { > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_neon_handler, > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_neon_handler, @@ -142,22 > +132,44 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len) > crc32_eth_lut); > } >=20 > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT static uint8_t > +sse42_pclmulqdq_cpu_supported(void) > +{ > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ); > +} > +#endif > + > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > +static uint8_t > +neon_pmull_cpu_supported(void) > +{ > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL); > +} > +#endif > + > void > rte_net_crc_set_alg(enum rte_net_crc_alg alg) { > switch (alg) { > -#ifdef X86_64_SSE42_PCLMULQDQ > +#ifdef RTE_ARCH_X86_64 > case RTE_NET_CRC_SSE42: > - handlers =3D handlers_sse42; > - break; > -#elif defined ARM64_NEON_PMULL > - /* fall-through */ > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > + if (sse42_pclmulqdq_cpu_supported()) { > + handlers =3D handlers_sse42; > + break; > + } > +#endif > +#endif /* RTE_ARCH_X86_64 */ > +#ifdef RTE_ARCH_ARM64 > case RTE_NET_CRC_NEON: > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > + if (neon_pmull_cpu_supported()) { > handlers =3D handlers_neon; > break; > } > #endif > +#endif /* RTE_ARCH_ARM64 */ > /* fall-through */ > case RTE_NET_CRC_SCALAR: > /* fall-through */ > @@ -188,11 +200,14 @@ RTE_INIT(rte_net_crc_init) >=20 > rte_net_crc_scalar_init(); >=20 > -#ifdef X86_64_SSE42_PCLMULQDQ > - alg =3D RTE_NET_CRC_SSE42; > - rte_net_crc_sse42_init(); > -#elif defined ARM64_NEON_PMULL > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > + if (sse42_pclmulqdq_cpu_supported()) { > + alg =3D RTE_NET_CRC_SSE42; > + rte_net_crc_sse42_init(); > + } > +#endif > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > + if (neon_pmull_cpu_supported()) { > alg =3D RTE_NET_CRC_NEON; > rte_net_crc_neon_init(); > } > -- > 2.12.3 Patch looks good to me except the one stated above. =20