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Wed, 24 Mar 2021 22:59:06 +0000 From: "Wang, Yipeng1" To: "Amber, Kumar" , "dev@dpdk.org" CC: "Richardson, Bruce" , Thomas Monjalon , "Gobriel, Sameh" Thread-Topic: [dpdk-dev] [PATCH v1] lib/hash: support non sse42 cpu architecture Thread-Index: AQHW6LVI+g6E+t6iEkKfpOQWbyf5S6qUL5eQ Date: Wed, 24 Mar 2021 22:59:06 +0000 Message-ID: References: <20210112072446.880122-1-kumar.amber@intel.com> In-Reply-To: <20210112072446.880122-1-kumar.amber@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [108.161.24.24] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dd4dc96a-eab9-43c4-f925-08d8ef186d2b x-ms-traffictypediagnostic: BYAPR11MB2791: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3494.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd4dc96a-eab9-43c4-f925-08d8ef186d2b X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Mar 2021 22:59:06.1757 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nuM6h7jDaDXr6js+9MEYMyKqZumVfFzTlw+fi/i8BfiUBYEFYfKhEXVhzO7ycFozZb/dz2EpgzOrW/wMwPgUVw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2791 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v1] lib/hash: support non sse42 cpu architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of kumar amber > Sent: Monday, January 11, 2021 11:25 PM > To: dev@dpdk.org > Cc: Richardson, Bruce > Subject: [dpdk-dev] [PATCH v1] lib/hash: support non sse42 cpu architectu= re >=20 > add _SSE42_ flag to enable compilation of > sse42 specific instructions only on supported architecture >=20 > Signed-off-by: kumar amber > --- > lib/librte_hash/rte_hash_crc.h | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) >=20 > diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_cr= c.h > index 3e131aa6bb..e9f063780c 100644 > --- a/lib/librte_hash/rte_hash_crc.h > +++ b/lib/librte_hash/rte_hash_crc.h > @@ -358,7 +358,7 @@ crc32c_2words(uint64_t data, uint32_t init_val) > return crc; > } >=20 > -#if defined(RTE_ARCH_X86) > +#if defined(RTE_ARCH_X86) && defined(__SSE42__) > static inline uint32_t > crc32c_sse42_u8(uint8_t data, uint32_t init_val) { @@ -404,7 +404,7 @@ > crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) } #endif ... > -#if defined RTE_ARCH_X86 > +#if defined(RTE_ARCH_X86) && defined(__SSE42__) > if (likely(crc32_alg & CRC32_SSE42)) > return crc32c_sse42_u64_mimic(data, init_val); #endif > -- > 2.25.1 [Wang, Yipeng]=20 Hi, Kumar, thanks for the patch. I think the minimum required machine for x86 is sse4.2 compatible already. = So I wonder if we really need this. Also, I think the right way to check machine flag in DPDK should be: #If defined (RTE_MACHINE_CPUFLAG_SSE4_2) Instead of using compiler dependent macro.