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Mon, 21 Sep 2020 09:03:40 +0000 From: "Jakub Grajciar -X (jgrajcia - PANTHEON TECH SRO at Cisco)" To: Honnappa Nagarahalli , Phil Yang , "dev@dpdk.org" CC: Ruifeng Wang , nd , nd Thread-Topic: [PATCH] net/memif: relax barrier for zero copy path Thread-Index: AQHWh/3EnG2VG7V/bUCs7pX4TLuPnKlvC/CAgAPLw9A= Date: Mon, 21 Sep 2020 09:03:38 +0000 Message-ID: References: <1599802699-20876-1-git-send-email-phil.yang@arm.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=cisco.com; x-originating-ip: [81.89.53.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e74d08a0-3fc3-4339-b3ae-08d85e0d3bb1 x-ms-traffictypediagnostic: BYAPR11MB3639: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: N3GLVxkVtabnhrHFId8kQLA2ZMbRR1EW2tO8pu6eXBhOegZbV2nUxy+M29Qv4xkFukdsqUWzU4U2nUrF86QIdRyIymXl/KE1/zDMZdr3iOvQQVA/jWqNJiG6UXefgJ03txIa6gCV860FxbvCnASOlFwom+nak/cqLks/ixwh7pIZ2MH5fR1Yhjkqe3sMEfCiD+otCXnuzXwV4ZDy0e3ILdA58LaB4JLyc8SxgM7/+rUlkAw+PsSBYMUEivQKzmJ2D8W6YGqt7a2VNzfkzNx859xkSgR/m/0gaJGR9laAYaJCTwk/KGOzB6Xs9HNDsSMOPjq2G7zViN5EdlTGNl5WUA== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e74d08a0-3fc3-4339-b3ae-08d85e0d3bb1 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2020 09:03:40.0343 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5ae1af62-9505-4097-a69a-c1553ef7840e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h0KG3wYpB2MZQKtbZHc4I2O2Ivu/2/s7abVOk1skXLhyfIoJiwmn1mFH6pLRJP20hPmyk2Ro5VfZxFz9NoWLdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3639 X-OriginatorOrg: cisco.com X-Outbound-SMTP-Client: 173.36.7.15, xch-aln-005.cisco.com X-Outbound-Node: rcdn-core-2.cisco.com Subject: Re: [dpdk-dev] [PATCH] net/memif: relax barrier for zero copy path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Honnappa, Inline comments... > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Saturday, September 19, 2020 12:49 AM > To: Phil Yang ; Jakub Grajciar -X (jgrajcia - PANTHEON > TECH SRO at Cisco) ; dev@dpdk.org > Cc: Ruifeng Wang ; nd ; Honnappa > Nagarahalli ; nd > Subject: RE: [PATCH] net/memif: relax barrier for zero copy path >=20 > Hi Jakub, > I am trying to review this patch. I am having difficulty in understandin= g > the implementation for the queue/ring, appreciate if you could help me > understand the logic. 'ring' refers to a ring buffer holding packet descriptors. These descriptor= s hold metadata about the packet (packet buffer address, length, etc..). 'queues' are a representation of rings and buffers (+ some metadata). In m= ore detail, one ring (S2M) and packet buffers allocated for this ring would= be represented as 'tx queue' for the slave and 'rx queue' for the master. >=20 > 1) The S2M queues - are used to send packets from slave to master. My > understanding is that, the slave thread would call 'eth_memif_tx_zc' and = the > master thread would call 'eth_memif_rx_zc'. Is this correct? > 2) The M2S queues - are used to send packets from master to slave. Here t= he > slave thread would call 'eth_memif_rx_zc' and the master thread would cal= l > 'eth_memif_tx_zc'. Is this correct? This is inded correct. >=20 > Thank you, > Honnappa >=20 > > -----Original Message----- > > From: Phil Yang > > Sent: Friday, September 11, 2020 12:38 AM > > To: jgrajcia@cisco.com; dev@dpdk.org > > Cc: Honnappa Nagarahalli ; Ruifeng Wang > > ; nd > > Subject: [PATCH] net/memif: relax barrier for zero copy path > > > > Using 'rte_mb' to synchronize the shared ring head/tail between > > producer and consumer will stall the pipeline and damage performance > > on the weak memory model platforms, such like aarch64. > > > > Relax the expensive barrier with c11 atomic with explicit memory > > ordering can improve 3.6% performance on throughput. My question here is: `rte_mb` is supposed to make sure that head/tail point= er are not updated before the packets are written into shared memory. Does = the atomic ensures that the packets are written into shared memory before h= ead/tail pointers are updated?