[PATCH] net/mlx5: reduce the counter pool name length

[PATCH] net/mlx5: reduce the counter pool name length

[Bing Zhao]

The name size of a rte_ring is RTE_MEMZONE_NAMESIZE with the value 32
by default. When creating a HWS counter pool cache, the final string
format was "RG_MLX5_HWS_CNT_POOL_%u_cache/%u" and it could support
less than 1000 variants. For example, if the first %u representing
port id is 100 and it will take all the available characters then the
second %u for queues will be discarded. If there was more than one
rule creation queue, the rte_ring could not be created.

By reducing the fixed character number and using hexadecimal format,
the issue can be overcome with an assumption that not all the integer
fields for queue index is used.

Fixes: 13ea6bdcc7ee ("net/mlx5: support counters in cross port shared mode")
Fixes: 4d368e1da3a4 ("net/mlx5: support flow counter action for HWS")
Cc: jackmin@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_hws_cnt.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c
index d98df68f39..18d80f34ba 100644
--- a/drivers/net/mlx5/mlx5_hws_cnt.c
+++ b/drivers/net/mlx5/mlx5_hws_cnt.c
@@ -419,8 +419,7 @@ mlx5_hws_cnt_pool_init(struct mlx5_dev_ctx_shared *sh,
 		goto error;
 	}
 	for (qidx = 0; qidx < ccfg->q_num; qidx++) {
-		snprintf(mz_name, sizeof(mz_name), "%s_cache/%u", pcfg->name,
-				qidx);
+		snprintf(mz_name, sizeof(mz_name), "%s_qc/%x", pcfg->name, qidx);
 		cntp->cache->qcache[qidx] = rte_ring_create(mz_name, ccfg->size,
 				SOCKET_ID_ANY,
 				RING_F_SP_ENQ | RING_F_SC_DEQ |
@@ -612,12 +611,10 @@ mlx5_hws_cnt_pool_create(struct rte_eth_dev *dev,
 	int ret = 0;
 	size_t sz;
 
-	mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0,
-			SOCKET_ID_ANY);
+	mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0, SOCKET_ID_ANY);
 	if (mp_name == NULL)
 		goto error;
-	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_POOL_%u",
-			dev->data->port_id);
+	snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_P_%x", dev->data->port_id);
 	pcfg.name = mp_name;
 	pcfg.request_num = pattr->nb_counters;
 	pcfg.alloc_factor = HWS_CNT_ALLOC_FACTOR_DEFAULT;
-- 
2.34.1

RE: [PATCH] net/mlx5: reduce the counter pool name length

[Raslan Darawsheh]

Hi,

> -----Original Message-----
> From: Bing Zhao <bingz@nvidia.com>
> Sent: Friday, June 30, 2023 3:58 PM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; Suanming Mou
> <suanmingm@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>
> Cc: dev@dpdk.org; Jack Min <jackmin@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] net/mlx5: reduce the counter pool name length
> 
> The name size of a rte_ring is RTE_MEMZONE_NAMESIZE with the value 32
> by default. When creating a HWS counter pool cache, the final string
> format was "RG_MLX5_HWS_CNT_POOL_%u_cache/%u" and it could support
> less than 1000 variants. For example, if the first %u representing
> port id is 100 and it will take all the available characters then the
> second %u for queues will be discarded. If there was more than one
> rule creation queue, the rte_ring could not be created.
> 
> By reducing the fixed character number and using hexadecimal format,
> the issue can be overcome with an assumption that not all the integer
> fields for queue index is used.
> 
> Fixes: 13ea6bdcc7ee ("net/mlx5: support counters in cross port shared
> mode")
> Fixes: 4d368e1da3a4 ("net/mlx5: support flow counter action for HWS")
> Cc: jackmin@nvidia.com
> Cc: stable@dpdk.org

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh