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From: Raslan Darawsheh <rasland@nvidia.com>
To: Dariusz Sosnowski <dsosnowski@nvidia.com>,
	Matan Azrad <matan@nvidia.com>,
	 Slava Ovsiienko <viacheslavo@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, "stable@dpdk.org" <stable@dpdk.org>
Subject: RE: [PATCH] net/mlx5: fix inline length for multi-segment TSO
Date: Wed, 9 Feb 2022 08:54:33 +0000	[thread overview]
Message-ID: <BYAPR12MB3078B55B595CFAD1AD610484CF2E9@BYAPR12MB3078.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20220207154856.574542-1-dsosnowski@nvidia.com>

Hi,

> -----Original Message-----
> From: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Sent: Monday, February 7, 2022 5:49 PM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>;
> stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix inline length for multi-segment TSO
> 
> This patch removes a redundant assert in mlx5_tx_packet_multi_tso().
> That assert assured that the amount of bytes requested to be inlined
> is greater than or equal to the minimum amount of bytes required
> to be inlined. This requirement is either derived from the NIC
> inlining mode or configured through devargs. When using TSO this
> requirement can be disregarded, because on all NICs it is satisfied by TSO
> inlining requirements, since TSO requires L2, L3, and L4 headers to be
> inlined.
> 
> Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
> Cc: viacheslavo@nvidia.com
> Cc: stable@dpdk.org
> 
> Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

      reply	other threads:[~2022-02-09  8:54 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-07 15:48 Dariusz Sosnowski
2022-02-09  8:54 ` Raslan Darawsheh [this message]

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