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From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
To: Stephen Hemminger <stephen@networkplumber.org>
CC: Adrien Mazarguil <adrien.mazarguil@6wind.com>, John McNamara
<john.mcnamara@intel.com>, Marko Kovacevic <marko.kovacevic@intel.com>,
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Thread-Topic: [EXT] Re: [dpdk-dev] [PATCH] ethdev: add HIGIG2 key field to
flow API
Thread-Index: AQHVg3g9PWQqqb+oIUW+ny3Ow/FI8KdcmLXw
Date: Wed, 16 Oct 2019 03:14:48 +0000
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Subject: Re: [dpdk-dev] [EXT] Re: [PATCH] ethdev: add HIGIG2 key field to
flow API
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Sender: "dev" <dev-bounces@dpdk.org>
> -----Original Message-----
> From: Stephen Hemminger <stephen@networkplumber.org>
> Sent: Tuesday, October 15, 2019 10:17 PM
> To: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
> Cc: Adrien Mazarguil <adrien.mazarguil@6wind.com>; John McNamara
> <john.mcnamara@intel.com>; Marko Kovacevic <marko.kovacevic@intel.com>;
> Thomas Monjalon <thomas@monjalon.net>; Ferruh Yigit
> <ferruh.yigit@intel.com>; Andrew Rybchenko <arybchenko@solarflare.com>;
> dev@dpdk.org; ajit.khaparde@broadcom.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH] ethdev: add HIGIG2 key field to flo=
w API
>=20
> External Email
>=20
> ----------------------------------------------------------------------
> On Mon, 14 Oct 2019 09:59:56 +0530
> <kirankumark@marvell.com> wrote:
>=20
> > +/**
> > + * RTE_FLOW_ITEM_TYPE_HIGIG2
> > + * Matches higig2 header.
> > + */
> > +struct rte_higig2_frc {
> > + uint32_t ksop:8;
> > + uint32_t resv:3;
> > + uint32_t mcst:1;
> > + uint32_t tc:4;
> > + uint32_t dst_modid:8;
> > + uint32_t dst_pid:8;
> > + uint32_t src_modid:8;
> > + uint32_t src_pid:8;
> > + uint32_t lbid:8;
> > + uint32_t dp:2;
> > + uint32_t resv1:3;
> > + uint32_t ppd_type:3;
> > +} __attribute__((packed));
> > +
> > +struct rte_higig2_ppt_type0 {
> > + uint32_t dst_t:1;
> > + uint32_t dst_tgid:3;
> > + uint32_t ingress_tagged:1;
> > + uint32_t mirror_only:1;
> > + uint32_t mirror_done:1;
> > + uint32_t mirror:1;
> > + uint32_t res:2;
> > + uint32_t l3:1;
> > + uint32_t label_present:1;
> > + uint32_t vc_label2:4;
> > + uint32_t vc_label1:8;
> > + uint32_t vc_label0:8;
> > + uint32_t vid_high:8;
> > + uint32_t vid_low:8;
> > + uint32_t pfm:2;
> > + uint32_t src_t:1;
> > + uint32_t res1:2;
> > + uint32_t opcode:3;
> > + uint32_t hdr_ext_len:3;
> > + uint32_t res2:5;
> > +} __attribute__((packed));
> > +
> > +struct rte_higig2_ppt_type1 {
> > + uint32_t classification:16;
> > + uint32_t resv:16;
> > + uint32_t vid:16;
> > + uint32_t pfm:2;
> > + uint32_t src_t:1;
> > + uint32_t resv1:2;
> > + uint32_t opcode:3;
> > + uint32_t hdr_ext_len:3;
> > + uint32_t resv2:5;
> > +} __attribute__((packed));
> > +
> > +RTE_STD_C11
> > +struct rte_flow_item_higig2_hdr {
> > + struct rte_higig2_frc fcr;
> > + union {
> > + struct rte_higig2_ppt_type0 ppt0;
> > + struct rte_higig2_ppt_type1 ppt1;
> > + };
> > +} __attribute__((packed));
> > +
> > +/** Default mask for RTE_FLOW_ITEM_TYPE_HIGIG2. */ #ifndef
> > +__cplusplus static const struct rte_flow_item_higig2_hdr
> > +rte_flow_item_higig2_hdr_mask =3D {
> > + .ppt1.classification =3D 0xffff,
> > + .ppt1.vid =3D 0xfff,
> > +};
> > +#endif
> > +
>=20
> Why do all these structures have to be packed. They are all uint32.
Will fix in V4.