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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 91db9063-c967-4f33-a02b-08d7196db0ee X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2019 06:25:20.5053 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2390 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-05_03:2019-07-31,2019-08-05 signatures=0 Subject: Re: [dpdk-dev] [PATCH] net/octeontx2: add 96xx A1 silicon revision support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Nithin Dabilpuram > Sent: Monday, August 5, 2019 11:11 AM > To: Jerin Jacob Kollanukkaran ; Nithin Kumar > Dabilpuram ; Vamsi Krishna Attunuru > ; Kiran Kumar Kokkilagadda > > Cc: dev@dpdk.org > Subject: [PATCH] net/octeontx2: add 96xx A1 silicon revision support >=20 > Update workaround changes for erratas that are fixed on 96xx A1. > This patch also enables cq drop for all the passes for maintaining > performance along with updating a default Rx ring size in dev_info. >=20 > Signed-off-by: Nithin Dabilpuram Acked-by: Jerin Jacob > --- > drivers/common/octeontx2/otx2_dev.h | 16 ++++++++++++++++ > drivers/net/octeontx2/otx2_ethdev.c | 29 +++++++++++++++++----------= - > - > drivers/net/octeontx2/otx2_ethdev.h | 7 +++++-- > drivers/net/octeontx2/otx2_ethdev_ops.c | 4 ++++ > drivers/net/octeontx2/otx2_flow_ctrl.c | 2 +- > 5 files changed, 43 insertions(+), 15 deletions(-) >=20 > diff --git a/drivers/common/octeontx2/otx2_dev.h > b/drivers/common/octeontx2/otx2_dev.h > index 53a3669..5fd05fa 100644 > --- a/drivers/common/octeontx2/otx2_dev.h > +++ b/drivers/common/octeontx2/otx2_dev.h > @@ -26,6 +26,22 @@ > #define otx2_dev_is_Ax(dev) \ > ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) =3D=3D 0x0)) >=20 > +#define otx2_dev_is_95xx_A0(dev) \ > + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) =3D=3D 0x1)) > +#define otx2_dev_is_95xx_Ax(dev) \ > + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) =3D=3D 0x1)) > + > +#define otx2_dev_is_96xx_A0(dev) \ > + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) =3D=3D 0x0)) > +#define otx2_dev_is_96xx_Ax(dev) \ > + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) =3D=3D 0x0) && \ > + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) =3D=3D 0x0)) > + > struct otx2_dev; >=20 > /* Link status callback */ > diff --git a/drivers/net/octeontx2/otx2_ethdev.c > b/drivers/net/octeontx2/otx2_ethdev.c > index 3fb7bd9..f151527 100644 > --- a/drivers/net/octeontx2/otx2_ethdev.c > +++ b/drivers/net/octeontx2/otx2_ethdev.c > @@ -266,26 +266,31 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct > otx2_eth_dev *dev, > aq->cq.cq_err_int_ena =3D BIT(NIX_CQERRINT_CQE_FAULT); > aq->cq.cq_err_int_ena |=3D BIT(NIX_CQERRINT_DOOR_ERR); >=20 > - /* TX pause frames enable flowctrl on RX side */ > - if (dev->fc_info.tx_pause) { > - /* Single bpid is allocated for all rx channels for now */ > - aq->cq.bpid =3D dev->fc_info.bpid[0]; > - aq->cq.bp =3D NIX_CQ_BP_LEVEL; > - aq->cq.bp_ena =3D 1; > - } > - > /* Many to one reduction */ > aq->cq.qint_idx =3D qid % dev->qints; > /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */ > aq->cq.cint_idx =3D qid; >=20 > if (otx2_ethdev_fixup_is_limit_cq_full(dev)) { > + const float rx_cq_skid =3D NIX_CQ_FULL_ERRATA_SKID; > uint16_t min_rx_drop; > - const float rx_cq_skid =3D 1024 * 256; >=20 > min_rx_drop =3D ceil(rx_cq_skid / (float)cq_size); > aq->cq.drop =3D min_rx_drop; > aq->cq.drop_ena =3D 1; > + rxq->cq_drop =3D min_rx_drop; > + } else { > + rxq->cq_drop =3D NIX_CQ_THRESH_LEVEL; > + aq->cq.drop =3D rxq->cq_drop; > + aq->cq.drop_ena =3D 1; > + } > + > + /* TX pause frames enable flowctrl on RX side */ > + if (dev->fc_info.tx_pause) { > + /* Single bpid is allocated for all rx channels for now */ > + aq->cq.bpid =3D dev->fc_info.bpid[0]; > + aq->cq.bp =3D rxq->cq_drop; > + aq->cq.bp_ena =3D 1; > } >=20 > rc =3D otx2_mbox_process(mbox); > @@ -324,8 +329,7 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct > otx2_eth_dev *dev, > /* Many to one reduction */ > aq->rq.qint_idx =3D qid % dev->qints; >=20 > - if (otx2_ethdev_fixup_is_limit_cq_full(dev)) > - aq->rq.xqe_drop_ena =3D 1; > + aq->rq.xqe_drop_ena =3D 1; >=20 > rc =3D otx2_mbox_process(mbox); > if (rc) { > @@ -1826,7 +1830,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) > dev->tx_offload_capa =3D nix_get_tx_offload_capa(dev); > dev->rx_offload_capa =3D nix_get_rx_offload_capa(dev); >=20 > - if (otx2_dev_is_Ax(dev)) { > + if (otx2_dev_is_96xx_A0(dev) || > + otx2_dev_is_95xx_Ax(dev)) { > dev->hwcap |=3D OTX2_FIXUP_F_MIN_4K_Q; > dev->hwcap |=3D OTX2_FIXUP_F_LIMIT_CQ_FULL; > } > diff --git a/drivers/net/octeontx2/otx2_ethdev.h > b/drivers/net/octeontx2/otx2_ethdev.h > index 720386f..6c3505c 100644 > --- a/drivers/net/octeontx2/otx2_ethdev.h > +++ b/drivers/net/octeontx2/otx2_ethdev.h > @@ -80,6 +80,7 @@ > #define NIX_CQ_ALIGN 512 > #define NIX_SQB_LOWER_THRESH 90 > #define LMT_SLOT_MASK 0x7f > +#define NIX_RX_DEFAULT_RING_SZ 4096 >=20 > /* If PTP is enabled additional SEND MEM DESC is required which > * takes 2 words, hence max 7 iova address are possible @@ -94,8 +95,9 @= @ > ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \ > + NIX_TX_NB_SEG_MAX) >=20 > -/* Apply BP when CQ is 75% full */ > -#define NIX_CQ_BP_LEVEL (25 * 256 / 100) > +/* Apply BP/DROP when CQ is 95% full */ > +#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100) > +#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) >=20 > #define CQ_OP_STAT_OP_ERR 63 > #define CQ_OP_STAT_CQ_ERR 46 > @@ -344,6 +346,7 @@ struct otx2_eth_rxq { > enum nix_q_size_e qsize; > struct rte_eth_dev *eth_dev; > struct otx2_eth_qconf qconf; > + uint16_t cq_drop; > } __rte_cache_aligned; >=20 > static inline struct otx2_eth_dev * > diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c > b/drivers/net/octeontx2/otx2_ethdev_ops.c > index 5a16a3c..8d0a3dc 100644 > --- a/drivers/net/octeontx2/otx2_ethdev_ops.c > +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c > @@ -431,6 +431,10 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, > struct rte_eth_dev_info *devinfo) > .offloads =3D 0, > }; >=20 > + devinfo->default_rxportconf =3D (struct rte_eth_dev_portconf) { > + .ring_size =3D NIX_RX_DEFAULT_RING_SZ, > + }; > + > devinfo->rx_desc_lim =3D (struct rte_eth_desc_lim) { > .nb_max =3D UINT16_MAX, > .nb_min =3D NIX_RX_MIN_DESC, > diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c > b/drivers/net/octeontx2/otx2_flow_ctrl.c > index ae56352..419ad97 100644 > --- a/drivers/net/octeontx2/otx2_flow_ctrl.c > +++ b/drivers/net/octeontx2/otx2_flow_ctrl.c > @@ -110,7 +110,7 @@ otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, > bool enb) > if (enb) { > aq->cq.bpid =3D fc->bpid[0]; > aq->cq_mask.bpid =3D ~(aq->cq_mask.bpid); > - aq->cq.bp =3D NIX_CQ_BP_LEVEL; > + aq->cq.bp =3D rxq->cq_drop; > aq->cq_mask.bp =3D ~(aq->cq_mask.bp); > } >=20 > -- > 2.8.4