From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 30F5929AC for ; Fri, 12 Apr 2019 08:07:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3C60XXT010288; Thu, 11 Apr 2019 23:07:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=XLcm8aSKi/9eMrF0P+Gk3HSSGhGL7FXohX7oOhxw+WI=; b=BMeVc103d/zvaMlJxa8oP/IaIyfbBvGX2TabudpqTKcJ0E3zf7MxA8bkLO8fkkRHbc+q fsQnbsWwU6UINKTuGzajw+7zCZA3LwYjXSArAAS03EfKiMXgT4g/aQMMPi1y0aEzjMV5 GiGjn2pHJd+oaKHgIeAh5TYdvVVN0zOc+/uHGsURUQm6QVeyfAnelZJDYLxGCtgLuXB/ A1M/Bc5gGfHrSH8VLChQEK8lYAlWHOmQBGeaOTHNjwhyS5clymm/7YCUpWGtKwyWR8Z9 AiTGv05zF/60dgaOa/N44eJCBrAP/raTiypfgTzrP81u5OKpLG3t2DNHsmHwp84WKGRG DQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2rt2xvbtcg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: THvd2Pi1zWFxBHWePGj1qZC7kLC4AlmA7X6LiTpVco95PuOm4A2ECpynor4wWJRYcLc3s9pMdC0ELNQtV/gOxT39kohcom8PFt6VAXCJV2TV0U9+QwA3GcSEHmu/nbUWqNTQuKzDGmIDVnkF6pYoFLmmf/zDsXqxCEyNQHN2OQDoIu132urabj8iv3p8VbuSPH8QE/eGdkPmPoPTGZtrAfnTb400+oDtO92BvrY+o3edNddMQB7mY2BGu0EYB81J0JiAKuAx1cuJGPljQ0yqRA9Bzj+QkbP2hbHdPHUTotL4rG7DmVcB1ltRoWPYHT7lQ0H46xMh4KNJ/VMZSeDAUwfY1vUSnEc36k6tWDcs6sawblMcf8A76xpIVwdwXsfJBGdVO7Sc9Iwptp+XXSqHFzGFBPcGyYb7HwyCNJffOLQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3835f60d-cd6b-4458-0a0f-08d6bf0d18d2 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 06:07:09.0211 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2661 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-12_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Apr 2019 06:07:13 -0000 > -----Original Message----- > From: Yongseok Koh > Sent: Friday, April 12, 2019 7:35 AM > To: Pavan Nikhilesh Bhagavatula > Cc: Thomas Monjalon ; dev ; Jerin > Jacob Kollanukkaran ; jerinjacobk@gmail.com > Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support > machine specific flags >=20 > External Email >=20 > I've tested it but still have an issue with old gcc. > Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either= . > So, it spews error due to lack of CRC feature. > -march should have '+crc'. The error I got was: >=20 > > ninja: Entering directory `build' > > [942/1452] Compiling C object > 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'. > > FAILED: > > > drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _a > > ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers > > -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic > > -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig > > -I../config-Ilib/librte_eal/common/include > > -I../lib/librte_eal/common/include > > -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common > > -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm > > -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal > > -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs > > -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf > > -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool > > -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline > > -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter > > -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux > > -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev > > -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline > > -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched > > -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag > > -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev > > -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni > > -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm > > -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe > > -D_FILE_OFFSET_BITS=3D64 -Wall -Winvalid-pch -O3 -include rte_config.h > > -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI > > MENTAL_API -MD -MQ > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o' -MF > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o.d' -o > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c > > {standard input}: Assembler messages: > > {standard input}:14: Error: selected processor does not support `crc32c= x > w3,w3,x0' > > {standard input}:37: Error: selected processor does not support `crc32c= x > w1,w1,x3' > > {standard input}:40: Error: selected processor does not support `crc32c= x > w0,w0,x2' >=20 >=20 > My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (R= ed > Hat 4.8.5-28)' Are you testing with very latest master where the following patch available= in build? http://patches.dpdk.org/patch/52367/ It should fix that issue. >=20 > Thanks, > Yongseok >=20 >=20 > > > >> > >> The command output check can also be removed as it is handled when > calling the command script itself. > > > > +1 > > > >> > >> Thoughts? > >> > >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache > >> type register[1] but sadly only few latest kernels have the support > >> through sysfs > >> (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) > > > > +1 > > > > In summary, +3. LoL > > > > I'll also submit a patch to change the default cacheline size of > > cortex-a72 with the new flags_*_extra[] > > > > > > thanks, > > Yongseok From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id BFFC9A0096 for ; Fri, 12 Apr 2019 08:07:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E6852BCE; Fri, 12 Apr 2019 08:07:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 30F5929AC for ; Fri, 12 Apr 2019 08:07:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3C60XXT010288; Thu, 11 Apr 2019 23:07:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: THvd2Pi1zWFxBHWePGj1qZC7kLC4AlmA7X6LiTpVco95PuOm4A2ECpynor4wWJRYcLc3s9pMdC0ELNQtV/gOxT39kohcom8PFt6VAXCJV2TV0U9+QwA3GcSEHmu/nbUWqNTQuKzDGmIDVnkF6pYoFLmmf/zDsXqxCEyNQHN2OQDoIu132urabj8iv3p8VbuSPH8QE/eGdkPmPoPTGZtrAfnTb400+oDtO92BvrY+o3edNddMQB7mY2BGu0EYB81J0JiAKuAx1cuJGPljQ0yqRA9Bzj+QkbP2hbHdPHUTotL4rG7DmVcB1ltRoWPYHT7lQ0H46xMh4KNJ/VMZSeDAUwfY1vUSnEc36k6tWDcs6sawblMcf8A76xpIVwdwXsfJBGdVO7Sc9Iwptp+XXSqHFzGFBPcGyYb7HwyCNJffOLQ= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3835f60d-cd6b-4458-0a0f-08d6bf0d18d2 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 06:07:09.0211 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2661 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-12_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190412060708.73rWQY_HTT9DtkH6otRYCmb3dUvIzOIwTuwBl829YhQ@z> > -----Original Message----- > From: Yongseok Koh > Sent: Friday, April 12, 2019 7:35 AM > To: Pavan Nikhilesh Bhagavatula > Cc: Thomas Monjalon ; dev ; Jerin > Jacob Kollanukkaran ; jerinjacobk@gmail.com > Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support > machine specific flags >=20 > External Email >=20 > I've tested it but still have an issue with old gcc. > Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either= . > So, it spews error due to lack of CRC feature. > -march should have '+crc'. The error I got was: >=20 > > ninja: Entering directory `build' > > [942/1452] Compiling C object > 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'. > > FAILED: > > > drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _a > > ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers > > -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic > > -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig > > -I../config-Ilib/librte_eal/common/include > > -I../lib/librte_eal/common/include > > -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common > > -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm > > -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal > > -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs > > -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf > > -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool > > -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline > > -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter > > -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux > > -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev > > -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline > > -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched > > -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag > > -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev > > -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni > > -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm > > -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe > > -D_FILE_OFFSET_BITS=3D64 -Wall -Winvalid-pch -O3 -include rte_config.h > > -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI > > MENTAL_API -MD -MQ > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o' -MF > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o.d' -o > > > 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic > _ > > action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c > > {standard input}: Assembler messages: > > {standard input}:14: Error: selected processor does not support `crc32c= x > w3,w3,x0' > > {standard input}:37: Error: selected processor does not support `crc32c= x > w1,w1,x3' > > {standard input}:40: Error: selected processor does not support `crc32c= x > w0,w0,x2' >=20 >=20 > My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (R= ed > Hat 4.8.5-28)' Are you testing with very latest master where the following patch available= in build? http://patches.dpdk.org/patch/52367/ It should fix that issue. >=20 > Thanks, > Yongseok >=20 >=20 > > > >> > >> The command output check can also be removed as it is handled when > calling the command script itself. > > > > +1 > > > >> > >> Thoughts? > >> > >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache > >> type register[1] but sadly only few latest kernels have the support > >> through sysfs > >> (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) > > > > +1 > > > > In summary, +3. LoL > > > > I'll also submit a patch to change the default cacheline size of > > cortex-a72 with the new flags_*_extra[] > > > > > > thanks, > > Yongseok