From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id CA140A0471 for ; Mon, 17 Jun 2019 11:19:24 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AF71A1BE94; Mon, 17 Jun 2019 11:19:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 463002E8F for ; Mon, 17 Jun 2019 11:19:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5H9B520006146 for ; Mon, 17 Jun 2019 02:19:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=BSn6+bsOuW1JUQ6PyR5N5qDYqSsOWICjqpTGeeaOm/0=; b=Qa6fvJ1VZXLSgYi3FmGFEy8mLb/teLkLjlGQGzBDkFHnWPgTowamqtFNkWqrJYIWJ2zA DgKY8ujaMI0fL1CbDrCFZFRAam/UtFv7ALIs+x3ajXYtv8rF+L0EqQij9+9SvR93IzvC +25t+TsKCCiBIH1t9lyY09msL/VfKUtXK+tkAGwXcrhyk2tH+PRCAjlku9XV62mckcG3 JQcRFQKAz59Tzb6dV/Sp97KN8i5W3YVqe1DAJa4D04eRrJAQbwsW3qHvg4dFoLCL2b9K 109Q07FFufTRvj9MSxqjL7yJUG2pD8/3WWIRA9XaUQ8nTmYgFwzpYAVk2oDfo9BQwElY xg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2t506hx0vr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 17 Jun 2019 02:19:21 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Mon, 17 Jun 2019 02:19:19 -0700 Received: from NAM01-SN1-obe.outbound.protection.outlook.com (104.47.32.56) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Mon, 17 Jun 2019 02:19:18 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BSn6+bsOuW1JUQ6PyR5N5qDYqSsOWICjqpTGeeaOm/0=; b=ty9s8nfNEuUDVTTASoHiuFCzRbTFgMhoUyIYoV39ep7nTR6PugQzrR9TdXL/6U+rx2EC+H0TVUxdw4pn2YfkpSRdQ9B8hZ72g4ZDHf4XcRvPirZQOLQ03YH1AFRBFN6n/9c5KqDiJ7GB8KInkiU2FPHxK28QV0PLnnLlo2s7Ybk= Received: from BYAPR18MB2424.namprd18.prod.outlook.com (20.179.91.149) by BYAPR18MB2918.namprd18.prod.outlook.com (20.179.59.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.10; Mon, 17 Jun 2019 09:19:17 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::75fd:a528:a1bf:bef4]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::75fd:a528:a1bf:bef4%3]) with mapi id 15.20.1987.014; Mon, 17 Jun 2019 09:19:17 +0000 From: Jerin Jacob Kollanukkaran To: Pavan Nikhilesh Bhagavatula , "Pavan Nikhilesh Bhagavatula" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 1/6] event/octeontx2: add event eth Rx adapter support Thread-Index: AQHVGffw1Tf6ijJ7YkC9uk6ICjOwVKafpuVQ Date: Mon, 17 Jun 2019 09:19:17 +0000 Message-ID: References: <20190603103429.814-1-pbhagavatula@marvell.com> <20190603103429.814-2-pbhagavatula@marvell.com> In-Reply-To: <20190603103429.814-2-pbhagavatula@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6eb3ba00-6235-4a2a-e0dc-08d6f304df7f x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:BYAPR18MB2918; x-ms-traffictypediagnostic: BYAPR18MB2918: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:489; x-forefront-prvs: 0071BFA85B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(39850400004)(346002)(376002)(366004)(136003)(199004)(189003)(13464003)(6436002)(71200400001)(71190400001)(76176011)(110136005)(25786009)(476003)(53546011)(229853002)(6506007)(55236004)(11346002)(9686003)(4326008)(6116002)(3846002)(478600001)(53936002)(7696005)(66476007)(446003)(102836004)(14454004)(55016002)(6246003)(76116006)(66946007)(73956011)(316002)(68736007)(66446008)(64756008)(66556008)(256004)(14444005)(30864003)(8676002)(81156014)(81166006)(8936002)(2906002)(74316002)(7736002)(86362001)(26005)(52536014)(186003)(99286004)(5660300002)(486006)(33656002)(6636002)(305945005)(66066001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2918; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: iH39p+BLIue5kA6vIrDuZh9+yYxrErF+/tFMt6mmtflXkhypRTP8XN2nZ/rgHNmvx5kBKtd3LkOL0M1lWq+2xd4ZnZyen4NqSWVgxf0BnVC3RuYut6T33yVylPQTqdvqTvDxoHTYspzuPOp9dTujbXDb7bECo851LHvPdZIHLeiYIBlkvvtpIwkEFqsOEP6ueLF/VwhBEvqzu3+bTfjt43METkmdxbS0amt/qjoHcMoQ5P4+4/95Ym+u1sOSLLGXNGw09Xhg+PUxnllMYhnC/3R7XuPZ2gAfyXePdv0AfpDZekDEemD7LtO8jf0E7iyHb6r7WX8NWz2yHdRpIKQDWAkrppyPP/pNi5y6rtyyAthFmsuN+wgv6GiUM03drol0aBvLrqoZ/wyOhCNVFKR/VhLudCEGNiD3otL/b3D0XOE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 6eb3ba00-6235-4a2a-e0dc-08d6f304df7f X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2019 09:19:17.3383 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2918 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-17_05:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 1/6] event/octeontx2: add event eth Rx adapter support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: pbhagavatula@marvell.com > Sent: Monday, June 3, 2019 4:04 PM > To: Jerin Jacob Kollanukkaran ; Pavan Nikhilesh > Bhagavatula > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 1/6] event/octeontx2: add event eth Rx adap= ter > support >=20 > From: Pavan Nikhilesh >=20 > Add event eth Rx adapter capabilities, queue add and delete functions. >=20 > Signed-off-by: Pavan Nikhilesh > Signed-off-by: Jerin Jacob > --- > drivers/event/octeontx2/Makefile | 4 +- > drivers/event/octeontx2/meson.build | 2 +- > drivers/event/octeontx2/otx2_evdev.c | 4 + > drivers/event/octeontx2/otx2_evdev.h | 15 ++ > drivers/event/octeontx2/otx2_evdev_adptr.c | 254 +++++++++++++++++++++ > 5 files changed, 276 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/event/octeontx2/Makefile > b/drivers/event/octeontx2/Makefile > index d01da6b11..20d7c2fee 100644 > --- a/drivers/event/octeontx2/Makefile > +++ b/drivers/event/octeontx2/Makefile > @@ -40,7 +40,7 @@ SRCS- > $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) +=3D > otx2_evdev_selftest.c > SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) +=3D > otx2_evdev_irq.c >=20 > LDLIBS +=3D -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs -LDLIBS +=3D = - > lrte_mempool -lrte_eventdev -lrte_mbuf -LDLIBS +=3D -lrte_common_octeontx= 2 - > lrte_mempool_octeontx2 > +LDLIBS +=3D -lrte_mempool -lrte_eventdev -lrte_mbuf -lrte_ethdev LDLIBS > ++=3D -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_pmd_octeontx2 As Ferruh suggested, We will remove the rte_pmd_octeontx2 dependency. >=20 > include $(RTE_SDK)/mk/rte.lib.mk > diff --git a/drivers/event/octeontx2/meson.build > b/drivers/event/octeontx2/meson.build > index bdb5beed6..e94bc5944 100644 > --- a/drivers/event/octeontx2/meson.build > +++ b/drivers/event/octeontx2/meson.build > @@ -26,4 +26,4 @@ foreach flag: extra_flags > endif > endforeach >=20 > -deps +=3D ['bus_pci', 'common_octeontx2', 'mempool_octeontx2'] > +deps +=3D ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', > +'pmd_octeontx2'] As Ferruh suggested, We will remove the rte_pmd_octeontx2 dependency. > diff --git a/drivers/event/octeontx2/o tx2_evdev.c > b/drivers/event/octeontx2/otx2_evdev.c > index 534ac4a6b..2ddc007f3 100644 > --- a/drivers/event/octeontx2/otx2_evdev.c > +++ b/drivers/event/octeontx2/otx2_evdev.c > @@ -1118,6 +1118,10 @@ static struct rte_eventdev_ops otx2_sso_ops =3D { > .port_unlink =3D otx2_sso_port_unlink, > .timeout_ticks =3D otx2_sso_timeout_ticks, >=20 > + .eth_rx_adapter_caps_get =3D otx2_sso_rx_adapter_caps_get, > + .eth_rx_adapter_queue_add =3D otx2_sso_rx_adapter_queue_add, > + .eth_rx_adapter_queue_del =3D otx2_sso_rx_adapter_queue_del, > + > .timer_adapter_caps_get =3D otx2_tim_caps_get, >=20 > .xstats_get =3D otx2_sso_xstats_get, > diff --git a/drivers/event/octeontx2/otx2_evdev.h > b/drivers/event/octeontx2/otx2_evdev.h > index eeb65f03f..d1e99b9d9 100644 > --- a/drivers/event/octeontx2/otx2_evdev.h > +++ b/drivers/event/octeontx2/otx2_evdev.h > @@ -6,9 +6,12 @@ > #define __OTX2_EVDEV_H__ >=20 > #include > +#include > +#include >=20 > #include "otx2_common.h" > #include "otx2_dev.h" > +#include "otx2_ethdev.h" > #include "otx2_mempool.h" >=20 > #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev @@ -234,6 > +237,18 @@ void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, > uint32_t event_type); > int sso_xae_reconfigure(struct rte_eventdev *event_dev); void > sso_fastpath_fns_set(struct rte_eventdev *event_dev); > + > +int otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev, > + const struct rte_eth_dev *eth_dev, > + uint32_t *caps); > +int otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev, > + const struct rte_eth_dev *eth_dev, > + int32_t rx_queue_id, > + const struct rte_event_eth_rx_adapter_queue_conf > *queue_conf); int > +otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, > + const struct rte_eth_dev *eth_dev, > + int32_t rx_queue_id); > + > /* Clean up API's */ > typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev); vo= id > ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id, diff --git > a/drivers/event/octeontx2/otx2_evdev_adptr.c > b/drivers/event/octeontx2/otx2_evdev_adptr.c > index 810722f89..1aef864fe 100644 > --- a/drivers/event/octeontx2/otx2_evdev_adptr.c > +++ b/drivers/event/octeontx2/otx2_evdev_adptr.c > @@ -4,6 +4,197 @@ >=20 > #include "otx2_evdev.h" >=20 > +int > +otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev, > + const struct rte_eth_dev *eth_dev, uint32_t *caps) { > + int rc; > + > + RTE_SET_USED(event_dev); > + rc =3D strncmp(eth_dev->device->driver->name, "net_octeontx2", 13); > + if (rc) > + *caps =3D RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; > + else > + *caps =3D RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT; > + > + return 0; > +} > + > +static inline int > +sso_rxq_enable(struct otx2_eth_dev *dev, uint16_t qid, uint8_t tt, uint8= _t > ggrp, > + uint16_t eth_port_id) > +{ > + struct otx2_mbox *mbox =3D dev->mbox; > + struct nix_aq_enq_req *aq; > + int rc; > + > + aq =3D otx2_mbox_alloc_msg_nix_aq_enq(mbox); > + aq->qidx =3D qid; > + aq->ctype =3D NIX_AQ_CTYPE_CQ; > + aq->op =3D NIX_AQ_INSTOP_WRITE; > + > + aq->cq.ena =3D 0; > + aq->cq.caching =3D 0; > + > + otx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s)); > + aq->cq_mask.ena =3D ~(aq->cq_mask.ena); > + aq->cq_mask.caching =3D ~(aq->cq_mask.caching); > + > + rc =3D otx2_mbox_process(mbox); > + if (rc < 0) { > + otx2_err("failed to disable cq context"); s/failed/Failed > + goto fail; > + } > + > + aq =3D otx2_mbox_alloc_msg_nix_aq_enq(mbox); > + aq->qidx =3D qid; > + aq->ctype =3D NIX_AQ_CTYPE_RQ; > + aq->op =3D NIX_AQ_INSTOP_WRITE; > + > + aq->rq.sso_ena =3D 1; > + aq->rq.sso_tt =3D tt; > + aq->rq.sso_grp =3D ggrp; > + aq->rq.ena_wqwd =3D 1; > + /* Mbuf Header generation : > + * > FIRST_SKIP is a super set of WQE_SKIP, dont modify first skip as > + * it already has data related to mbuf size, headroom, private area. > + * > Using WQE_SKIP we can directly assign > + * mbuf =3D wqe - sizeof(struct mbuf); > + * so that mbuf header will not have unpredicted values while headroom > + * and private data starts at the begining of wqe_data. > + */ > + aq->rq.wqe_skip =3D 1; > + aq->rq.wqe_caching =3D 1; > + aq->rq.spb_ena =3D 0; > + aq->rq.flow_tagw =3D 20; /* 20-bits */ > + > + /* Flow Tag calculation : > + * > + * rq_tag <31:24> =3D good/bad_tag<8:0>; > + * rq_tag <23:0> =3D [ltag] > + * > + * flow_tag_mask<31:0> =3D (1 << flow_tagw) - 1; <31:20> > + * tag<31:0> =3D (~flow_tag_mask & rq_tag) | (flow_tag_mask & > flow_tag); > + * > + * Setup : > + * ltag<23:0> =3D (eth_port_id & 0xF) << 20; > + * good/bad_tag<8:0> =3D > + * ((eth_port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV << 4); > + * > + * TAG<31:0> on getwork =3D <31:28>(RTE_EVENT_TYPE_ETHDEV) | > + * <27:20> (eth_port_id) | <20:0> [TAG] > + */ > + > + aq->rq.ltag =3D (eth_port_id & 0xF) << 20; > + aq->rq.good_utag =3D ((eth_port_id >> 4) & 0xF) | > + (RTE_EVENT_TYPE_ETHDEV << 4); > + aq->rq.bad_utag =3D aq->rq.good_utag; > + > + aq->rq.ena =3D 1; > + aq->rq.pb_caching =3D 0x2; /* First cache aligned block to LLC */ > + aq->rq.xqe_imm_size =3D 0; /* No pkt data copy to CQE */ > + > + otx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s)); > + /* mask the bits to write. */ > + aq->rq_mask.sso_ena =3D ~(aq->rq_mask.sso_ena); > + aq->rq_mask.sso_tt =3D ~(aq->rq_mask.sso_tt); > + aq->rq_mask.sso_grp =3D ~(aq->rq_mask.sso_grp); > + aq->rq_mask.ena_wqwd =3D ~(aq->rq_mask.ena_wqwd); > + aq->rq_mask.wqe_skip =3D ~(aq->rq_mask.wqe_skip); > + aq->rq_mask.wqe_caching =3D ~(aq->rq_mask.wqe_caching); > + aq->rq_mask.spb_ena =3D ~(aq->rq_mask.spb_ena); > + aq->rq_mask.flow_tagw =3D ~(aq->rq_mask.flow_tagw); > + aq->rq_mask.ltag =3D ~(aq->rq_mask.ltag); > + aq->rq_mask.good_utag =3D ~(aq->rq_mask.good_utag); > + aq->rq_mask.bad_utag =3D ~(aq->rq_mask.bad_utag); > + aq->rq_mask.ena =3D ~(aq->rq_mask.ena); > + aq->rq_mask.pb_caching =3D ~(aq->rq_mask.pb_caching); > + aq->rq_mask.xqe_imm_size =3D ~(aq->rq_mask.xqe_imm_size); > + > + rc =3D otx2_mbox_process(mbox); > + if (rc < 0) { > + otx2_err("failed to init rx adapter context"); s/failed/Failed > + goto fail; > + } > + > + return 0; > +fail: > + return rc; > +} > + > +static inline int > +sso_rxq_disable(struct otx2_eth_dev *dev, uint16_t qid) { > + struct otx2_mbox *mbox =3D dev->mbox; > + struct nix_aq_enq_req *aq; > + int rc; > + > + aq =3D otx2_mbox_alloc_msg_nix_aq_enq(mbox); > + aq->qidx =3D qid; > + aq->ctype =3D NIX_AQ_CTYPE_CQ; > + aq->op =3D NIX_AQ_INSTOP_INIT; > + > + aq->cq.ena =3D 1; > + aq->cq.caching =3D 1; > + > + otx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s)); > + aq->cq_mask.ena =3D ~(aq->cq_mask.ena); > + aq->cq_mask.caching =3D ~(aq->cq_mask.caching); > + > + rc =3D otx2_mbox_process(mbox); > + if (rc < 0) { > + otx2_err("failed to init cq context"); s/failed/Failed > + goto fail; > + } > + > + aq =3D otx2_mbox_alloc_msg_nix_aq_enq(mbox); > + aq->qidx =3D qid; > + aq->ctype =3D NIX_AQ_CTYPE_RQ; > + aq->op =3D NIX_AQ_INSTOP_WRITE; > + > + aq->rq.sso_ena =3D 0; > + aq->rq.sso_tt =3D SSO_TT_UNTAGGED; > + aq->rq.sso_grp =3D 0; > + aq->rq.ena_wqwd =3D 0; > + aq->rq.wqe_caching =3D 0; > + aq->rq.wqe_skip =3D 0; > + aq->rq.spb_ena =3D 0; > + aq->rq.flow_tagw =3D 0x20; > + aq->rq.ltag =3D 0; > + aq->rq.good_utag =3D 0; > + aq->rq.bad_utag =3D 0; > + aq->rq.ena =3D 1; > + aq->rq.pb_caching =3D 0x2; /* First cache aligned block to LLC */ > + aq->rq.xqe_imm_size =3D 0; /* No pkt data copy to CQE */ > + > + otx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s)); > + /* mask the bits to write. */ > + aq->rq_mask.sso_ena =3D ~(aq->rq_mask.sso_ena); > + aq->rq_mask.sso_tt =3D ~(aq->rq_mask.sso_tt); > + aq->rq_mask.sso_grp =3D ~(aq->rq_mask.sso_grp); > + aq->rq_mask.ena_wqwd =3D ~(aq->rq_mask.ena_wqwd); > + aq->rq_mask.wqe_caching =3D ~(aq->rq_mask.wqe_caching); > + aq->rq_mask.wqe_skip =3D ~(aq->rq_mask.wqe_skip); > + aq->rq_mask.spb_ena =3D ~(aq->rq_mask.spb_ena); > + aq->rq_mask.flow_tagw =3D ~(aq->rq_mask.flow_tagw); > + aq->rq_mask.ltag =3D ~(aq->rq_mask.ltag); > + aq->rq_mask.good_utag =3D ~(aq->rq_mask.good_utag); > + aq->rq_mask.bad_utag =3D ~(aq->rq_mask.bad_utag); > + aq->rq_mask.ena =3D ~(aq->rq_mask.ena); > + aq->rq_mask.pb_caching =3D ~(aq->rq_mask.pb_caching); > + aq->rq_mask.xqe_imm_size =3D ~(aq->rq_mask.xqe_imm_size); > + > + rc =3D otx2_mbox_process(mbox); > + if (rc < 0) { > + otx2_err("failed to clear rx adapter context"); s/failed/Failed > + goto fail; > + } > + > + return 0; > +fail: > + return rc; > +} > + > void > sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, uint32_t > event_type) { @@ -17,3 +208,66 @@ sso_updt_xae_cnt(struct otx2_sso_evdev > *dev, void *data, uint32_t event_type) > break; > } > } > 2.21.0