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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2456; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: CLsr+3Bsyn+Ax4S9wOrxv1NSr9krguLTvsXBPq9HnwnmoSUZtF2If90HuPBs95i0kq6SQHvb4O05140Sfi56C1M0dx6AknFe8UZso2qKN+h3nfYhzSvU+/KN6/ouQ0eu/ofulKgBhkKC3qqbnHB4XACTOYTd1fKX7mBKQnkXqxvd1yImcHcvbZFlwcUQm/BiJ3qytA00lJmUV+KlNjpWD1mp6cXv+Rb3VT69pgz+utmgb3pfYiN4jtlJfxBP5gS1v6Vevu4oZHva9LNJ0d04OtqAiZOVYx5DOoAH0Xd1j2KHLlRfaESFUZAtPdA8hOH0JJffYc1ODbaSDTTtuyjfF+szLJUVBRLh+6QtXrJato7nrOeDaVy3Hojpuqdd8d0WstvMW9ijTqEpT5TGye0jk6hof964ovpovR8OMUuwyUc= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: b7d2bd73-f4e7-443e-a1ec-08d71030d79a X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jul 2019 12:17:05.6175 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2456 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-24_05:2019-07-24,2019-07-24 signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 4/5] spinlock: use wfe to reduce contention on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Gavin Hu > Sent: Tuesday, July 23, 2019 9:14 PM > To: dev@dpdk.org > Cc: nd@arm.com; thomas@monjalon.net; stephen@networkplumber.org; > Jerin Jacob Kollanukkaran ; Pavan Nikhilesh > Bhagavatula ; > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com > Subject: [EXT] [PATCH v3 4/5] spinlock: use wfe to reduce contention on > aarch64 >=20 > In acquiring a spinlock, cores repeatedly poll the lock variable. > This is replaced by rte_wait_until_equal API. >=20 > 5~10% performance gain was measured by running spinlock_autotest on > 14 isolated cores of ThunderX2. >=20 > Signed-off-by: Gavin Hu > Reviewed-by: Ruifeng Wang > Reviewed-by: Phil Yang > Reviewed-by: Steve Capper > Reviewed-by: Ola Liljedahl > Reviewed-by: Honnappa Nagarahalli > Tested-by: Pavan Nikhilesh > --- > .../common/include/arch/arm/rte_spinlock.h | 25 > ++++++++++++++++++++++ > .../common/include/generic/rte_spinlock.h | 2 +- > 2 files changed, 26 insertions(+), 1 deletion(-) >=20 > diff --git a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h > b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h > index 1a6916b..f25d17f 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h > @@ -16,6 +16,31 @@ extern "C" { > #include > #include "generic/rte_spinlock.h" >=20 > +/* armv7a does support WFE, but an explicit wake-up signal using SEV is > + * required (must be preceded by DSB to drain the store buffer) and > + * this is less performant, so keep armv7a implementation unchanged. > + */ > +#if defined(RTE_USE_WFE) && defined(RTE_ARCH_ARM64) static inline See below. Please avoid complicated conditional compilation logic for scala= bility and readability. =20 > void > +rte_spinlock_lock(rte_spinlock_t *sl) { > + unsigned int tmp; > + /* http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc. > + * faqs/ka16809.html > + */ > + asm volatile( > + "sevl\n" > + "1: wfe\n" > + "2: ldaxr %w[tmp], %w[locked]\n" > + "cbnz %w[tmp], 1b\n" > + "stxr %w[tmp], %w[one], %w[locked]\n" > + "cbnz %w[tmp], 2b\n" > + : [tmp] "=3D&r" (tmp), [locked] "+Q"(sl->locked) > + : [one] "r" (1) > + : "cc", "memory"); > +} > +#endif > + > static inline int rte_tm_supported(void) { > return 0; > diff --git a/lib/librte_eal/common/include/generic/rte_spinlock.h > b/lib/librte_eal/common/include/generic/rte_spinlock.h > index 87ae7a4..cf4f15b 100644 > --- a/lib/librte_eal/common/include/generic/rte_spinlock.h > +++ b/lib/librte_eal/common/include/generic/rte_spinlock.h > @@ -57,7 +57,7 @@ rte_spinlock_init(rte_spinlock_t *sl) static inline vo= id > rte_spinlock_lock(rte_spinlock_t *sl); >=20 > -#ifdef RTE_FORCE_INTRINSICS > +#if defined(RTE_FORCE_INTRINSICS) && !defined(RTE_USE_WFE) I would like to avoid hacking around adjusting generic code to meet specifi= c requirement. For example, if someone enables RTE_USE_WFE for armv7 it will break And it will pain for the new architecture to use RTE_FORCE_INTRINSICS. Looks like the time has come to disable RTE_FORCE_INTRINSICS for arm64.=20 Since this patch is targeted for next release. How about enable native Implementation for RTE_FORCE_INTRINSICS used code for arm64 like spinlock, = ticketlock like x86. If you guys don't have the bandwidth to convert all blocks, let us know, we= can collaborate and Marvell can take up some RTE_FORCE_INTRINSICS conversion for next relea= se. > static inline void > rte_spinlock_lock(rte_spinlock_t *sl) > { > -- > 2.7.4