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Thu, 11 Apr 2019 20:12:09 +0000 From: Yongseok Koh <yskoh@mellanox.com> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> CC: Thomas Monjalon <thomas@monjalon.net>, dev <dev@dpdk.org>, Jerin Jacob Kollanukkaran <jerinj@marvell.com>, "jerinjacobk@gmail.com" <jerinjacobk@gmail.com> Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWAgADReACAAOv/AA== Date: Thu, 11 Apr 2019 20:12:09 +0000 Message-ID: <C4F41778-F0F3-49A5-8472-E307FF57BFFB@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> <CY4PR1801MB186361CD95AF5D519FBF93F5DE2F0@CY4PR1801MB1863.namprd18.prod.outlook.com> In-Reply-To: <CY4PR1801MB186361CD95AF5D519FBF93F5DE2F0@CY4PR1801MB1863.namprd18.prod.outlook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3961; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7UCT7G3zvJ88452AMzbquBkN7AkeAw9UnhIJVt2/xVefzUtOrdDPHVYgBE3f4dDyosCmKoVnTNxSexMqKGV5DlP8sph0m2CuCB1ZrTP9dvbcOjgHLCwflxoGLnc8o2G0Xym9YioUxkURf6ltpDScFFQhRyDLdZhWbbJ/aeUnKYJd4t/GMMZtv34Uc50bkY2dygmbWUzyZDV/3wsQVHKXx8N9OLumojs9yxAu/LA51MOs9t+eVavcf7QyugECaUe57Xd0qMFOvcEkgxJGSv9GbWMw94aWJvmz0rIJt20t6mIWEs0WgVna+1Ob8Bv3yj0wvEdv11EoMkhZdpQl6rtSFcAByfAQj3LP/Q4rOj/5YpPYz7A7UVlmnpKf/Sca9C0hK58IDVBpioef3z1oTNO/x3pQMH12nvAsuoe1Kl8mEww= Content-Type: text/plain; charset="us-ascii" Content-ID: <45119A637116DE44AADBF2F24220D391@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91d84a0e-a12c-4f06-39a9-08d6beb9fa45 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2019 20:12:09.4620 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3961 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Thu, 11 Apr 2019 20:12:12 -0000 > On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@m= arvell.com> wrote: >=20 > Hi Yongseok, >=20 >> -----Original Message----- >> From: Yongseok Koh <yskoh@mellanox.com> >> Sent: Wednesday, April 10, 2019 11:08 PM >> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> >> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin >> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com >> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support >> machine specific flags >>=20 >> External Email >>=20 >> ---------------------------------------------------------------------- >>=20 >>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >>>=20 >>> From: Pavan Nikhilesh <pbhagavatula@marvell.com> >>>=20 >>> Currently, RTE_* flags are set based on the implementer ID but there >>> might be some micro arch specific differences from the same vendor eg. >>> CACHE_LINESIZE. Add support to set micro arch specific flags. >>>=20 >>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> >>> Signed-off-by: Jerin Jacob <jerinj@marvell.com> >>> --- >>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >>> 1 file changed, 32 insertions(+), 24 deletions(-) >>>=20 >>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>> 170a4981a..24bce2b39 100644 >>> --- a/config/arm/meson.build >>> +++ b/config/arm/meson.build >>> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >>>=20 >>> arm_force_native_march =3D false >>>=20 >>> -machine_args_generic =3D [ >>> - ['default', ['-march=3Darmv8-a+crc+crypto']], >>> - ['native', ['-march=3Dnative']], >>> - ['0xd03', ['-mcpu=3Dcortex-a53']], >>> - ['0xd04', ['-mcpu=3Dcortex-a35']], >>> - ['0xd05', ['-mcpu=3Dcortex-a55']], >>> - ['0xd07', ['-mcpu=3Dcortex-a57']], >>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>> - ['0xd09', ['-mcpu=3Dcortex-a73']], >>> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >>> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >>> -] >>> -machine_args_cavium =3D [ >>> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>> - ['native', ['-march=3Dnative']], >>> - ['0xa1', ['-mcpu=3Dthunderxt88']], >>> - ['0xa2', ['-mcpu=3Dthunderxt81']], >>> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >>> - >>> flags_common_default =3D [ >>> # Accelarate rte_memcpy. Be sure to run unit test >> (memcpy_perf_autotest) >>> # to determine the best threshold in code. Refer to notes in source >>> file @@ -52,12 +33,10 @@ flags_generic =3D [ >>> ['RTE_USE_C11_MEM_MODEL', true], >>> ['RTE_CACHE_LINE_SIZE', 128]] >>> flags_cavium =3D [ >>> - ['RTE_MACHINE', '"thunderx"'], >>> ['RTE_CACHE_LINE_SIZE', 128], >>> ['RTE_MAX_NUMA_NODES', 2], >>> ['RTE_MAX_LCORE', 96], >>> - ['RTE_MAX_VFIO_GROUPS', 128], >>> - ['RTE_USE_C11_MEM_MODEL', false]] >>> + ['RTE_MAX_VFIO_GROUPS', 128]] >>> flags_dpaa =3D [ >>> ['RTE_MACHINE', '"dpaa"'], >>> ['RTE_USE_C11_MEM_MODEL', true], >>> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >>> ['RTE_MAX_NUMA_NODES', 1], >>> ['RTE_MAX_LCORE', 16], >>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >>> +flags_default_extra =3D [] >>> +flags_thunderx_extra =3D [ >>> + ['RTE_MACHINE', '"thunderx"'], >>> + ['RTE_USE_C11_MEM_MODEL', false]] >>> + >>> +machine_args_generic =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xd03', ['-mcpu=3Dcortex-a53']], >>> + ['0xd04', ['-mcpu=3Dcortex-a35']], >>> + ['0xd07', ['-mcpu=3Dcortex-a57']], >>> + ['0xd08', ['-mcpu=3Dcortex-a72']], >>> + ['0xd09', ['-mcpu=3Dcortex-a73']], >>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>> + >>> +machine_args_cavium =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >>>=20 >>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>> machine_args_generic] @@ -157,8 +157,16 @@ else >>> endif >>> foreach marg: machine[2] >>> if marg[0] =3D=3D impl_pn >>> - foreach f: marg[1] >>> - machine_args +=3D f >>> + foreach flag: marg[1] >>> + if cc.has_argument(flag) >>> + machine_args +=3D flag >>> + endif >>> + endforeach >>> + # Apply any extra machine specific flags. >>> + foreach flag: marg.get(2, flags_default_extra) >>> + if flag.length() > 0 >>> + dpdk_conf.set(flag[0], flag[1]) >>> + endif >>=20 >> Let me continue the discussion from v7 here. >> Seems I wan't clear enough. >>=20 >> Let me take an example. If the host is thunderx2 (0xaf) and compiler is = older >> than v7, flags_thunderx2_extra isn't set. This means, for example, >> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you migh= t >> want to set it regardless of gcc version. You could skip setting -mcpu w= ith setting >> the extra flags. >>=20 >=20 > Thanks for the detailed explanation. > I think since we have the check to skip mcpu flag when cc doesn't support= it (cc.has_argument(flag)) > It will be safe to remove=20 > ` > # Primary part number based mcpu flags are supported > # for gcc versions > 7 > if cc.version().version_compare( > '<7.0') or cmd_output.length() =3D=3D 0 > if not meson.is_cross_build() and arm_force_native_march = =3D=3D true > impl_pn =3D 'native' > else > impl_pn =3D 'default' > endif > endif > ` +1 >=20 > The command output check can also be removed as it is handled when callin= g the command script itself. +1 >=20 > Thoughts? >=20 > PS. I think the safest way to set CACHELINE_SIZE is to read the cache typ= e register[1] but sadly only few latest kernels=20 > have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0= /coherency_line_size)=20 +1 In summary, +3. LoL I'll also submit a patch to change the default cacheline size of cortex-a72= with the new flags_*_extra[] thanks, Yongseok= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 61D3AA0096 for <public@inbox.dpdk.org>; Thu, 11 Apr 2019 22:12:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70F984CC3; Thu, 11 Apr 2019 22:12:13 +0200 (CEST) Received: from EUR02-VE1-obe.outbound.protection.outlook.com (mail-eopbgr20077.outbound.protection.outlook.com [40.107.2.77]) by dpdk.org (Postfix) with ESMTP id F28FF2BCE for <dev@dpdk.org>; Thu, 11 Apr 2019 22:12:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fzpU/1oXeDDAMZlF3fOGYygF4g6um7a7t13Ec7oz1CU=; b=pHH1/LbxgNn2EW2SmnaZbVupsd4UDzP1khK88gLqfHlQxrWg3lLRZWo+GyNduB0h9H4QPGxgfLYNyRP3oP+a/8UND967psD4feaiqu+QqARBy5KZlsHn/GlXB/y3LW0DFAI18vCS7PwNiFMven1QzKtCBunLh+4yj5Cb3GNlYAw= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3961.eurprd05.prod.outlook.com (52.134.70.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1771.18; Thu, 11 Apr 2019 20:12:09 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Thu, 11 Apr 2019 20:12:09 +0000 From: Yongseok Koh <yskoh@mellanox.com> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> CC: Thomas Monjalon <thomas@monjalon.net>, dev <dev@dpdk.org>, Jerin Jacob Kollanukkaran <jerinj@marvell.com>, "jerinjacobk@gmail.com" <jerinjacobk@gmail.com> Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWAgADReACAAOv/AA== Date: Thu, 11 Apr 2019 20:12:09 +0000 Message-ID: <C4F41778-F0F3-49A5-8472-E307FF57BFFB@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> <CY4PR1801MB186361CD95AF5D519FBF93F5DE2F0@CY4PR1801MB1863.namprd18.prod.outlook.com> In-Reply-To: <CY4PR1801MB186361CD95AF5D519FBF93F5DE2F0@CY4PR1801MB1863.namprd18.prod.outlook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3961; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7UCT7G3zvJ88452AMzbquBkN7AkeAw9UnhIJVt2/xVefzUtOrdDPHVYgBE3f4dDyosCmKoVnTNxSexMqKGV5DlP8sph0m2CuCB1ZrTP9dvbcOjgHLCwflxoGLnc8o2G0Xym9YioUxkURf6ltpDScFFQhRyDLdZhWbbJ/aeUnKYJd4t/GMMZtv34Uc50bkY2dygmbWUzyZDV/3wsQVHKXx8N9OLumojs9yxAu/LA51MOs9t+eVavcf7QyugECaUe57Xd0qMFOvcEkgxJGSv9GbWMw94aWJvmz0rIJt20t6mIWEs0WgVna+1Ob8Bv3yj0wvEdv11EoMkhZdpQl6rtSFcAByfAQj3LP/Q4rOj/5YpPYz7A7UVlmnpKf/Sca9C0hK58IDVBpioef3z1oTNO/x3pQMH12nvAsuoe1Kl8mEww= Content-Type: text/plain; charset="UTF-8" Content-ID: <45119A637116DE44AADBF2F24220D391@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91d84a0e-a12c-4f06-39a9-08d6beb9fa45 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2019 20:12:09.4620 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3961 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Message-ID: <20190411201209.PIVgfZFeyykEUdmjidOjtPH6I5cWOcj5Gj5jAoNYlss@z> > On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@m= arvell.com> wrote: >=20 > Hi Yongseok, >=20 >> -----Original Message----- >> From: Yongseok Koh <yskoh@mellanox.com> >> Sent: Wednesday, April 10, 2019 11:08 PM >> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> >> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin >> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com >> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support >> machine specific flags >>=20 >> External Email >>=20 >> ---------------------------------------------------------------------- >>=20 >>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >>>=20 >>> From: Pavan Nikhilesh <pbhagavatula@marvell.com> >>>=20 >>> Currently, RTE_* flags are set based on the implementer ID but there >>> might be some micro arch specific differences from the same vendor eg. >>> CACHE_LINESIZE. Add support to set micro arch specific flags. >>>=20 >>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> >>> Signed-off-by: Jerin Jacob <jerinj@marvell.com> >>> --- >>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >>> 1 file changed, 32 insertions(+), 24 deletions(-) >>>=20 >>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>> 170a4981a..24bce2b39 100644 >>> --- a/config/arm/meson.build >>> +++ b/config/arm/meson.build >>> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >>>=20 >>> arm_force_native_march =3D false >>>=20 >>> -machine_args_generic =3D [ >>> - ['default', ['-march=3Darmv8-a+crc+crypto']], >>> - ['native', ['-march=3Dnative']], >>> - ['0xd03', ['-mcpu=3Dcortex-a53']], >>> - ['0xd04', ['-mcpu=3Dcortex-a35']], >>> - ['0xd05', ['-mcpu=3Dcortex-a55']], >>> - ['0xd07', ['-mcpu=3Dcortex-a57']], >>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>> - ['0xd09', ['-mcpu=3Dcortex-a73']], >>> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >>> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >>> -] >>> -machine_args_cavium =3D [ >>> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>> - ['native', ['-march=3Dnative']], >>> - ['0xa1', ['-mcpu=3Dthunderxt88']], >>> - ['0xa2', ['-mcpu=3Dthunderxt81']], >>> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >>> - >>> flags_common_default =3D [ >>> # Accelarate rte_memcpy. Be sure to run unit test >> (memcpy_perf_autotest) >>> # to determine the best threshold in code. Refer to notes in source >>> file @@ -52,12 +33,10 @@ flags_generic =3D [ >>> ['RTE_USE_C11_MEM_MODEL', true], >>> ['RTE_CACHE_LINE_SIZE', 128]] >>> flags_cavium =3D [ >>> - ['RTE_MACHINE', '"thunderx"'], >>> ['RTE_CACHE_LINE_SIZE', 128], >>> ['RTE_MAX_NUMA_NODES', 2], >>> ['RTE_MAX_LCORE', 96], >>> - ['RTE_MAX_VFIO_GROUPS', 128], >>> - ['RTE_USE_C11_MEM_MODEL', false]] >>> + ['RTE_MAX_VFIO_GROUPS', 128]] >>> flags_dpaa =3D [ >>> ['RTE_MACHINE', '"dpaa"'], >>> ['RTE_USE_C11_MEM_MODEL', true], >>> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >>> ['RTE_MAX_NUMA_NODES', 1], >>> ['RTE_MAX_LCORE', 16], >>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >>> +flags_default_extra =3D [] >>> +flags_thunderx_extra =3D [ >>> + ['RTE_MACHINE', '"thunderx"'], >>> + ['RTE_USE_C11_MEM_MODEL', false]] >>> + >>> +machine_args_generic =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xd03', ['-mcpu=3Dcortex-a53']], >>> + ['0xd04', ['-mcpu=3Dcortex-a35']], >>> + ['0xd07', ['-mcpu=3Dcortex-a57']], >>> + ['0xd08', ['-mcpu=3Dcortex-a72']], >>> + ['0xd09', ['-mcpu=3Dcortex-a73']], >>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>> + >>> +machine_args_cavium =3D [ >>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>> + ['native', ['-march=3Dnative']], >>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >>>=20 >>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>> machine_args_generic] @@ -157,8 +157,16 @@ else >>> endif >>> foreach marg: machine[2] >>> if marg[0] =3D=3D impl_pn >>> - foreach f: marg[1] >>> - machine_args +=3D f >>> + foreach flag: marg[1] >>> + if cc.has_argument(flag) >>> + machine_args +=3D flag >>> + endif >>> + endforeach >>> + # Apply any extra machine specific flags. >>> + foreach flag: marg.get(2, flags_default_extra) >>> + if flag.length() > 0 >>> + dpdk_conf.set(flag[0], flag[1]) >>> + endif >>=20 >> Let me continue the discussion from v7 here. >> Seems I wan't clear enough. >>=20 >> Let me take an example. If the host is thunderx2 (0xaf) and compiler is = older >> than v7, flags_thunderx2_extra isn't set. This means, for example, >> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you migh= t >> want to set it regardless of gcc version. You could skip setting -mcpu w= ith setting >> the extra flags. >>=20 >=20 > Thanks for the detailed explanation. > I think since we have the check to skip mcpu flag when cc doesn't support= it (cc.has_argument(flag)) > It will be safe to remove=20 > ` > # Primary part number based mcpu flags are supported > # for gcc versions > 7 > if cc.version().version_compare( > '<7.0') or cmd_output.length() =3D=3D 0 > if not meson.is_cross_build() and arm_force_native_march = =3D=3D true > impl_pn =3D 'native' > else > impl_pn =3D 'default' > endif > endif > ` +1 >=20 > The command output check can also be removed as it is handled when callin= g the command script itself. +1 >=20 > Thoughts? >=20 > PS. I think the safest way to set CACHELINE_SIZE is to read the cache typ= e register[1] but sadly only few latest kernels=20 > have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0= /coherency_line_size)=20 +1 In summary, +3. LoL I'll also submit a patch to change the default cacheline size of cortex-a72= with the new flags_*_extra[] thanks, Yongseok=