From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id BD4767CA9 for ; Mon, 4 Sep 2017 12:04:03 +0200 (CEST) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Sep 2017 03:04:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,474,1498546800"; d="scan'208";a="125369204" Received: from irsmsx153.ger.corp.intel.com ([163.33.192.75]) by orsmga004.jf.intel.com with ESMTP; 04 Sep 2017 03:04:00 -0700 Received: from irsmsx109.ger.corp.intel.com ([169.254.13.28]) by IRSMSX153.ger.corp.intel.com ([169.254.9.34]) with mapi id 14.03.0319.002; Mon, 4 Sep 2017 11:03:59 +0100 From: "Burakov, Anatoly" To: Markus Theil , "dev@dpdk.org" CC: "Yigit, Ferruh" , "stephen@networkplumber.org" Thread-Topic: [dpdk-dev] [PATCH v5 4/5] igb_uio: use msi mask functions from kernel, little corrections Thread-Index: AQHTIqLOYeITUaphCkGr5TX6dTO2uqKkhKhQ Date: Mon, 4 Sep 2017 10:03:58 +0000 Message-ID: References: <1504174949-25656-3-git-send-email-markus.theil@tu-ilmenau.de> <1504216020-16067-1-git-send-email-markus.theil@tu-ilmenau.de> <1504216020-16067-4-git-send-email-markus.theil@tu-ilmenau.de> In-Reply-To: <1504216020-16067-4-git-send-email-markus.theil@tu-ilmenau.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_PUBLIC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzg4MGU0OGItNmY4My00MmZkLTllMjgtNTk1MDc0ZGExOGIwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX1BVQkxJQyJ9XX1dfSwiU3ViamVjdExhYmVscyI6W10sIlRNQ1ZlcnNpb24iOiIxNi41LjkuMyIsIlRydXN0ZWRMYWJlbEhhc2giOiJFaG9hdDFDUlFORGY4MzUyc2twcnRFdjBEaUh4QTBNeTZPamF6eVArbE5BPSJ9 dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v5 4/5] igb_uio: use msi mask functions from kernel, little corrections X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Sep 2017 10:04:04 -0000 Hi Markus, > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Markus Theil > Sent: Thursday, August 31, 2017 10:47 PM > To: dev@dpdk.org > Cc: Yigit, Ferruh ; stephen@networkplumber.org; > Markus Theil > Subject: [dpdk-dev] [PATCH v5 4/5] igb_uio: use msi mask functions from > kernel, little corrections >=20 > This patch substitutes the custom MSI/MSI-X mask code and uses already > existing kernel APIs. Feedback/small corrections to the previous patch of= this > series are also incorporated. >=20 > Signed-off-by: Markus Theil > --- > lib/librte_eal/linuxapp/igb_uio/compat.h | 26 +++------ > lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 88 ++++++++------------------= ----- > 2 files changed, 31 insertions(+), 83 deletions(-) >=20 > diff --git a/lib/librte_eal/linuxapp/igb_uio/compat.h > b/lib/librte_eal/linuxapp/igb_uio/compat.h > index 3825933..67a7ab3 100644 > --- a/lib/librte_eal/linuxapp/igb_uio/compat.h > +++ b/lib/librte_eal/linuxapp/igb_uio/compat.h > @@ -15,24 +15,6 @@ > #define HAVE_PTE_MASK_PAGE_IOMAP > #endif >=20 > -#ifndef PCI_MSIX_ENTRY_SIZE > -#define PCI_MSIX_ENTRY_SIZE 16 > -#define PCI_MSIX_ENTRY_LOWER_ADDR 0 > -#define PCI_MSIX_ENTRY_UPPER_ADDR 4 > -#define PCI_MSIX_ENTRY_DATA 8 > -#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 > -#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 > -#endif > - > -/* > - * for kernels < 2.6.38 and backported patch that moves MSI-X entry > definition > - * to pci_regs.h Those kernels has PCI_MSIX_ENTRY_SIZE defined but not > - * PCI_MSIX_ENTRY_CTRL_MASKBIT > - */ > -#ifndef PCI_MSIX_ENTRY_CTRL_MASKBIT > -#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 > -#endif > - > #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34) && \ > (!(defined(RHEL_RELEASE_CODE) && \ > RHEL_RELEASE_CODE >=3D RHEL_RELEASE_VERSION(5, 9))) @@ -127,3 > +109,11 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev) #if > LINUX_VERSION_CODE >=3D KERNEL_VERSION(4, 8, 0) #define > HAVE_ALLOC_IRQ_VECTORS 1 #endif > + > +#if LINUX_VERSION_CODE >=3D KERNEL_VERSION(3, 19, 0) #define > +HAVE_PCI_MSI_MASK_IRQ 1 #endif > + > +#if LINUX_VERSION_CODE >=3D KERNEL_VERSION(2, 6, 37) #define > +HAVE_IRQ_DATA 1 #endif > diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > index 99a085a..5830453 100644 > --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > @@ -92,51 +92,6 @@ static const struct attribute_group dev_attr_grp =3D { > .attrs =3D dev_attrs, > }; >=20 > -/* > - * It masks the msix on/off of generating MSI-X messages. > - */ > -static void > -igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state) -{ > - u32 mask_bits =3D desc->masked; > - unsigned offset =3D desc->msi_attrib.entry_nr * > PCI_MSIX_ENTRY_SIZE + > - > PCI_MSIX_ENTRY_VECTOR_CTRL; > - > - if (state !=3D 0) > - mask_bits &=3D ~PCI_MSIX_ENTRY_CTRL_MASKBIT; > - else > - mask_bits |=3D PCI_MSIX_ENTRY_CTRL_MASKBIT; > - > - if (mask_bits !=3D desc->masked) { > - writel(mask_bits, desc->mask_base + offset); > - readl(desc->mask_base); > - desc->masked =3D mask_bits; > - } > -} > - > -/* > - * It masks the msi on/off of generating MSI messages. > - */ > -static void > -igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t > state) -{ > - u32 mask_bits =3D desc->masked; > - u32 offset =3D desc->irq - pdev->irq; > - u32 mask =3D 1 << offset; > - u32 flag =3D !!state << offset; > - > - if (!desc->msi_attrib.maskbit) > - return; > - > - mask_bits &=3D ~mask; > - mask_bits |=3D flag; > - > - if (mask_bits !=3D desc->masked) { > - pci_write_config_dword(pdev, desc->mask_pos, mask_bits); > - desc->masked =3D mask_bits; > - } > -} > - > /** > * This is the irqcontrol callback to be registered to uio_info. > * It can be used to disable/enable interrupt from user space processes. > @@ -156,31 +111,31 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 > irq_state) > struct rte_uio_pci_dev *udev =3D info->priv; > struct pci_dev *pdev =3D udev->pdev; >=20 > - pci_cfg_access_lock(pdev); > - if (udev->mode =3D=3D RTE_INTR_MODE_LEGACY) > - pci_intx(pdev, !!irq_state); > - > - else if (udev->mode =3D=3D RTE_INTR_MODE_MSIX) { > - struct msi_desc *desc; > - > -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) > - list_for_each_entry(desc, &pdev->msi_list, list) > - igbuio_msix_mask_irq(desc, irq_state); > +#ifdef HAVE_IRQ_DATA > + struct irq_data *irq =3D irq_get_irq_data(udev->info.irq); > #else > - list_for_each_entry(desc, &pdev->dev.msi_list, list) > - igbuio_msix_mask_irq(desc, irq_state); > + unsigned int irq =3D udev->info.irq; > #endif > - } else if (udev->mode =3D=3D RTE_INTR_MODE_MSI) { > - struct msi_desc *desc; >=20 > -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) > - list_for_each_entry(desc, &pdev->msi_list, list) > - igbuio_msi_mask_irq(pdev, desc, irq_state); > + pci_cfg_access_lock(pdev); > + > + if (udev->mode =3D=3D RTE_INTR_MODE_MSIX || udev->mode =3D=3D > +RTE_INTR_MODE_MSI) { #ifdef HAVE_PCI_MSI_MASK_IRQ > + if (irq_state =3D=3D 1) > + pci_msi_unmask_irq(irq); > + else > + pci_msi_mask_irq(irq); > #else > - list_for_each_entry(desc, &pdev->dev.msi_list, list) > - igbuio_msi_mask_irq(pdev, desc, irq_state); > + if (irq_state =3D=3D 1) > + unmask_msi_irq(irq); > + else > + mask_msi_irq(irq); > #endif > } > + > + if (udev->mode =3D=3D RTE_INTR_MODE_LEGACY) > + pci_intx(pdev, !!irq_state); > + > pci_cfg_access_unlock(pdev); >=20 > return 0; > @@ -365,11 +320,13 @@ igbuio_pci_enable_interrupts(struct > rte_uio_pci_dev *udev) #else > if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) =3D=3D > 1) { > dev_dbg(&udev->pdev->dev, "using MSI-X"); > + udev->info.irq_flags =3D IRQF_NO_THREAD; This (and similar below) looks like unrelated changes. Should probably be i= n a separate patch, with their own justifications. Thanks, Anatoly > udev->info.irq =3D pci_irq_vector(udev->pdev, 0); > udev->mode =3D RTE_INTR_MODE_MSIX; > break; > } > #endif > + /* fall back to MSI */ > case RTE_INTR_MODE_MSI: > #ifndef HAVE_ALLOC_IRQ_VECTORS > if (pci_enable_msi(udev->pdev) =3D=3D 0) { @@ -382,6 +339,7 > @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev) #else > if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) =3D=3D > 1) { > dev_dbg(&udev->pdev->dev, "using MSI"); > + udev->info.irq_flags =3D IRQF_NO_THREAD; > udev->info.irq =3D pci_irq_vector(udev->pdev, 0); > udev->mode =3D RTE_INTR_MODE_MSI; > break; > @@ -397,7 +355,7 @@ igbuio_pci_enable_interrupts(struct rte_uio_pci_dev > *udev) > break; > } > dev_notice(&udev->pdev->dev, "PCI INTX mask not > supported\n"); > - /* fall back to no IRQ */ > + /* fall back to no IRQ */ > case RTE_INTR_MODE_NONE: > udev->mode =3D RTE_INTR_MODE_NONE; > udev->info.irq =3D 0; > -- > 2.7.4