From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f66.google.com (mail-ed1-f66.google.com [209.85.208.66]) by dpdk.org (Postfix) with ESMTP id 36E6E2BF1 for ; Fri, 10 Aug 2018 09:51:50 +0200 (CEST) Received: by mail-ed1-f66.google.com with SMTP id o8-v6so4296072edt.13 for ; Fri, 10 Aug 2018 00:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=g7GQWPti9hx0Z3nJzlbMan6/mD/HMzSYf3HFp4pWsFw=; b=Jp6XPhcKGaLz8I+W5QcJbmurSEWH5+tJLiN/GzP003Gj9kzIjgJrrSLKtqoFJ5okgG sMrBcPN5YVLlC+Yfk24Z7ZZ/Px+N3QmEWsUX+UaKS6QtFtrMtsHqYBNrPYW29SX/YmaY hgbbGSXnm1slGlgH+X+QY+kpPv4Uz7moThVzf5mxucLjCMtUim/mSd89zT6yFzAlzPjS rZK0y107wCvO7cY8ZaTT2l03JqGV0BRYLikFeucMLaaVf6Xt8kV482u7gxPbD+2MqlV2 l2varanG2GReudAMcCQSKfacIDgVc8/RMUJ9goxibywexUFEgGtgz+c4FkrOTfg9BeFf qEIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=g7GQWPti9hx0Z3nJzlbMan6/mD/HMzSYf3HFp4pWsFw=; b=HOxwixrJqjDhPwjV2mo+3gq760012YSdDhnGvGoIbOvcINKcCsCX2FUfD6vacOGqvn ICGnrda0IMZxgMuSzJvyhHW4ibE5rYD869r33Mft5nomNbDE5KPw1fT8c5IqG849kRuo Oaowsp3KshfwWxlk5kG3Nj32BPRko/QXptQba1WPkRMun3yu63DnExeBJD52vKS619tb xGVWqTsAKL7oco0CK8f8MA1T1ZMhuOIV8aliY1DlWyVBuwYUiOz1E/+9aptuXhiU8GJ+ lIFbv5U9NJ1yRK7zOL8mHrsch+1ly6xQuomZ2rldP3UhketTD+hyXfTJxywnApj7HRvN 905w== X-Gm-Message-State: AOUpUlGgW1Qf+HH75M4zFUY+BUIdvoHB5SFcJR94g9ZbZUxuTIMs/65J dIPdO1+kwYRwFpZV7G1Czov06f+4+UaK8cYrsRU= X-Google-Smtp-Source: AA+uWPxM6OiXMmSj6QtiRE/FvFC3rwf6/9raZrAffrNTZQkdn6qPYzSbZJUjZRjIdfFxG6JV0AQvLv3CthVKIO0mqhs= X-Received: by 2002:a50:c251:: with SMTP id t17-v6mr7073399edf.108.1533887509890; Fri, 10 Aug 2018 00:51:49 -0700 (PDT) MIME-Version: 1.0 References: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> <6dae8866-3df9-fa11-ab08-cb553a80102a@intel.com> In-Reply-To: <6dae8866-3df9-fa11-ab08-cb553a80102a@intel.com> From: Drocula Date: Fri, 10 Aug 2018 15:51:38 +0800 Message-ID: To: "Burakov, Anatoly" Cc: maxime.coquelin@redhat.com, dev@dpdk.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH] bus/pci: check if 5-level paging is enabled when testing IOMMU address width X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Aug 2018 07:51:50 -0000 Thanks, will refine in v2. On Thu, Aug 9, 2018, 18:49 Burakov, Anatoly wrote: > On 05-Aug-18 7:41 PM, Drocula wrote: > > The kernel version 4.14 released with the support of 5-level paging. > > When PML5 enabled, user-space virtual addresses uses up to 56 bits. > > see kernel's Documentation/x86/x86_64/mm.txt. > > > > Signed-off-by: Drocula > > --- > > drivers/bus/pci/linux/pci.c | 27 +++++++++++++++++++++++++-- > > 1 file changed, 25 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c > > index 004600f..8913d6d 100644 > > --- a/drivers/bus/pci/linux/pci.c > > +++ b/drivers/bus/pci/linux/pci.c > > @@ -4,6 +4,7 @@ > > > > #include > > #include > > +#include > > > > #include > > #include > > @@ -553,12 +554,34 @@ > > } > > > > #if defined(RTE_ARCH_X86) > > +/* > > + * Try to detect whether the system uses 5-level page table. > > + */ > > +static bool > > +system_uses_PML5(void) > > +{ > > + void *page_4k, *mask = (void *)0xf0000000000000; > > + page_4k = mmap(mask, 4096, PROT_READ | PROT_WRITE, > > + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); > > + > > + if (page_4k == (void *) -1) > > + return false; > > Shouldn't this be MAP_FAILED? > > > + munmap(page_4k, 4096); > > + > > + if ((unsigned long)page_4k & (unsigned long)mask) > > + return true; > > + return false; > > +} > > + > > static bool > > pci_one_device_iommu_support_va(struct rte_pci_device *dev) > > { > > #define VTD_CAP_MGAW_SHIFT 16 > > #define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) > > -#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ > > +/* From Documentation/x86/x86_64/mm.txt */ > > +#define X86_VA_WIDTH_PML4 47 > > +#define X86_VA_WIDTH_PML5 56 > > + > > struct rte_pci_addr *addr = &dev->addr; > > char filename[PATH_MAX]; > > FILE *fp; > > @@ -589,7 +612,7 @@ > > fclose(fp); > > > > mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + > 1; > > - if (mgaw < X86_VA_WIDTH) > > + if (mgaw < (system_uses_PML5() ? X86_VA_WIDTH_PML5 : > X86_VA_WIDTH_PML4)) > > This is perhaps nitpicking and a question of personal preferences, but i > think storing this in a var would be more readable than doing ternary > operator inside of an if statement. > > > return false; > > > > return true; > > > > > -- > Thanks, > Anatoly >