From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk0-f68.google.com (mail-vk0-f68.google.com [209.85.213.68]) by dpdk.org (Postfix) with ESMTP id 8F7A02BE5 for ; Tue, 23 Jan 2018 15:14:51 +0100 (CET) Received: by mail-vk0-f68.google.com with SMTP id h69so369752vke.7 for ; Tue, 23 Jan 2018 06:14:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=aXHdZILL7EcO772l+DUgpb7lExoNhiQ+aLOdmXQ+5/I=; b=tCkWvUQKrcOxpf0zFtkcuKB8PeXgpwc1d0JoOoGhNTCsqmsTQAVbFbLJbQ5FXufMV6 JFd6kz05K7Bo5W5xPYeHWy5VUCn5yS2CxekgSs+MgRui60MrGC393ov3kU0BGIdDsoGN IYuOwHLhjNUL8j/Ew6oWA/DBdtcvumMo7gI0zla/eikKKEnl3IdgAmCD553m8a7m9rvZ LyW2up8y1/b57xdS35S7Zu8zyIoItwwHULhYulJJIX2js9ou/6BzFLnh/Yp0iso/pY6k EjFl5JJD/tZn5vSlwIbFoKGpLKw9gRuoQpl46FXdVXZfaE2MfrFWZ+cAd5m/04cV+TLJ HQqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=aXHdZILL7EcO772l+DUgpb7lExoNhiQ+aLOdmXQ+5/I=; b=na9PMh4wmViL9xMrvaiqvU5v5jjxErgeB+odkgZlFh4TFdg7dH4r/wYYQbkjD5CKJo 0h0rqljGsA+wBIpULhBvpAaJgS8CFRH2qulDFW4HubXRdeNLHOKc8zt40eFGjtgUi01s s+fYtXHz5x/yEaSC1Z5XzhI+Tpv00LIcel/fieUVif6KJ1VMNxpfKz8fDEJcr3swA2bd raF1q3gL0sEzOjtkqRnz07gpZ759tvsg7w/OwxhRF/c326qNPI2TsHT7QxD8Ltx406kH yz43LUI9TixVXxQuxTpQ4n0jdEjJzwxik3p8XqCIsUWswX2uD4+3Zds2PoN+AgH8UZs+ Oqzg== X-Gm-Message-State: AKwxytf/2lw8gJPeOph2emunscMtUIJJWn+VKuP4hG8sB+cJRIQRGUBM YxVKOJpqLGTmFIcbnPIJx+ZC84+cgQWMzPnNGEA= X-Google-Smtp-Source: AH8x225J2FFKnJEXWbyGWFrMqlxWpMEUWzFxJCZ2Q1+fVjhjqkcJLbRJzgiCv3sG5AL+faga2wee0evx8SPHURO78d4= X-Received: by 10.31.221.131 with SMTP id u125mr1518702vkg.80.1516716890977; Tue, 23 Jan 2018 06:14:50 -0800 (PST) MIME-Version: 1.0 Received: by 10.176.13.144 with HTTP; Tue, 23 Jan 2018 06:14:50 -0800 (PST) In-Reply-To: References: <1509978323-9879-1-git-send-email-shweta.choudaha@gmail.com> <1509978323-9879-2-git-send-email-shweta.choudaha@gmail.com> From: Shweta Choudaha Date: Tue, 23 Jan 2018 14:14:50 +0000 Message-ID: To: "Zhang, Helin" Cc: "dev@dpdk.org" , "Kirsher, Jeffrey T" , "Greenwalt, Paul" , "Tantilov, Emil S" , "Nguyen, Anthony L" , Shweta Choudaha , "Lu, Wenzhuo" , "Ananyev, Konstantin" , "Dai, Wei" , "Wu, Jingjing" , "Zhang, Qi Z" Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Jan 2018 14:14:51 -0000 Hi Helin, Thanks for the review. Yes , the backplane interfaces(x550em) does not have a phy connected but it still MDIO lines for control. The requirement for us is to be able to access phy registers over backplane MDIO . I 've an updated patchset which is cleaner. I 'll send that for review. Thanks, Shweta On Wed, Jan 10, 2018 at 3:17 AM, Zhang, Helin wrote: > > > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > > Sent: Monday, November 6, 2017 10:25 PM > > To: dev@dpdk.org > > Cc: Shweta Choudaha > > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO > support > > > > From: Shweta Choudaha > > > > Initialize MDIO read/write functions for backplan port > > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO > > > > Signed-off-by: Shweta Choudaha > > Reviewed-by: Chas Williams > > Reviewed-by: Luca Boccassi > > --- > > drivers/net/ixgbe/base/ixgbe_x550.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > > b/drivers/net/ixgbe/base/ixgbe_x550.c > > index 9862391..3f89dc4 100644 > > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw > > *hw) > > } > > > > switch (hw->device_id) { > > + case IXGBE_DEV_ID_X550EM_A_KR_L: > Basically this device ID is for a specific SoC platform, there is no > external PHY for it. > We prefer to NACK it. I added more experts here to answer more questions > if you have. > Note that they are not working on DPDK, and they are experts on ixgbe > NIC/SW. > Or we can discuss more if you have any requests to Intel. > > Sorry, > Helin > > > case IXGBE_DEV_ID_X550EM_A_1G_T: > > case IXGBE_DEV_ID_X550EM_A_1G_T_L: > > phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; > > -- > > 2.1.4 > >