* [dpdk-dev] [PATCH 1/2] net/ixgbe: add and export MDIO APIs @ 2017-11-06 13:42 Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 " Shweta Choudaha 0 siblings, 1 reply; 10+ messages in thread From: Shweta Choudaha @ 2017-11-06 13:42 UTC (permalink / raw) To: dev; +Cc: bluca Add ixgbe MDIO access APIs to read and write PHY registers when being used as a backplane port. Export these APIs via the map file Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> Reviewed-by: Chas Williams <chas3@att.com> Reviewed-by: Luca Boccassi <bluca@debian.org> --- drivers/net/ixgbe/rte_pmd_ixgbe.c | 53 +++++++++++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe.h | 39 +++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 7 ++++ 3 files changed, 99 insertions(+) diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c index f127378..34d8cb4 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c @@ -1041,3 +1041,56 @@ rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id) return ixgbe_bypass_wd_reset(dev); } #endif + +static void rte_pmd_ixgbe_get_hw_phy(uint16_t port, struct ixgbe_hw **hw, + struct ixgbe_phy_info **phy) +{ + struct rte_eth_dev *dev; + + *hw = NULL; + *phy = NULL; + + dev = &rte_eth_devices[port]; + if (!is_ixgbe_supported(dev)) + return; + + *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (!*hw) + return; + + *phy = &(*hw)->phy; +} + +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.read_reg_mdi(hw, reg_addr, dev_type, phy_data); +} + +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.write_reg_mdi(hw, reg_addr, dev_type, phy_data); +} diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h b/drivers/net/ixgbe/rte_pmd_ixgbe.h index 81b18f8..5d36f8a 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h @@ -601,6 +601,45 @@ int rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t *wd_timeout); */ int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port); +/** + * Read PHY register using MDIO + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always Unused + * @param phy_data + * Pointer for reading PHY register data + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data); + +/** + * Write data to PHY register using MDIO + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always unused + * @param phy_data + * Data to write to PHY register + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data); /** * Response sent back to ixgbe driver from user app after callback diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map index bf77674..b4d5983 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map @@ -52,3 +52,10 @@ DPDK_17.08 { rte_pmd_ixgbe_bypass_wd_timeout_show; rte_pmd_ixgbe_bypass_wd_timeout_store; } DPDK_17.05; + +EXPERIMENTAL { + global: + + rte_pmd_ixgbe_mdio_read; + rte_pmd_ixgbe_mdio_write; +} DPDK_17.11; -- 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs 2017-11-06 13:42 [dpdk-dev] [PATCH 1/2] net/ixgbe: add and export MDIO APIs Shweta Choudaha @ 2017-11-06 14:25 ` Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha ` (2 more replies) 0 siblings, 3 replies; 10+ messages in thread From: Shweta Choudaha @ 2017-11-06 14:25 UTC (permalink / raw) To: dev; +Cc: Shweta Choudaha From: Shweta Choudaha <shweta.choudaha@att.com> Add ixgbe MDIO access APIs to read and write PHY registers when being used as a backplane port. Export these APIs via the map file Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> Reviewed-by: Chas Williams <chas3@att.com> Reviewed-by: Luca Boccassi <bluca@debian.org> --- drivers/net/ixgbe/rte_pmd_ixgbe.c | 53 +++++++++++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe.h | 39 +++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 7 ++++ 3 files changed, 99 insertions(+) diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c index f127378..34d8cb4 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c @@ -1041,3 +1041,56 @@ rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id) return ixgbe_bypass_wd_reset(dev); } #endif + +static void rte_pmd_ixgbe_get_hw_phy(uint16_t port, struct ixgbe_hw **hw, + struct ixgbe_phy_info **phy) +{ + struct rte_eth_dev *dev; + + *hw = NULL; + *phy = NULL; + + dev = &rte_eth_devices[port]; + if (!is_ixgbe_supported(dev)) + return; + + *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (!*hw) + return; + + *phy = &(*hw)->phy; +} + +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.read_reg_mdi(hw, reg_addr, dev_type, phy_data); +} + +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.write_reg_mdi(hw, reg_addr, dev_type, phy_data); +} diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h b/drivers/net/ixgbe/rte_pmd_ixgbe.h index 81b18f8..5d36f8a 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h @@ -601,6 +601,45 @@ int rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t *wd_timeout); */ int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port); +/** + * Read PHY register using MDIO + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always Unused + * @param phy_data + * Pointer for reading PHY register data + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data); + +/** + * Write data to PHY register using MDIO + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always unused + * @param phy_data + * Data to write to PHY register + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data); /** * Response sent back to ixgbe driver from user app after callback diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map index bf77674..ce72c73 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map @@ -52,3 +52,10 @@ DPDK_17.08 { rte_pmd_ixgbe_bypass_wd_timeout_show; rte_pmd_ixgbe_bypass_wd_timeout_store; } DPDK_17.05; + +EXPERIMENTAL { + global: + + rte_pmd_ixgbe_mdio_read; + rte_pmd_ixgbe_mdio_write; +} DPDK_17.08; -- 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 " Shweta Choudaha @ 2017-11-06 14:25 ` Shweta Choudaha 2017-12-21 3:23 ` Zhang, Helin 2018-01-10 3:17 ` Zhang, Helin 2017-12-21 3:25 ` [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs Zhang, Helin 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 " Shweta Choudaha 2 siblings, 2 replies; 10+ messages in thread From: Shweta Choudaha @ 2017-11-06 14:25 UTC (permalink / raw) To: dev; +Cc: Shweta Choudaha From: Shweta Choudaha <shweta.choudaha@att.com> Initialize MDIO read/write functions for backplan port (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> Reviewed-by: Chas Williams <chas3@att.com> Reviewed-by: Luca Boccassi <bluca@debian.org> --- drivers/net/ixgbe/base/ixgbe_x550.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index 9862391..3f89dc4 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) } switch (hw->device_id) { + case IXGBE_DEV_ID_X550EM_A_KR_L: case IXGBE_DEV_ID_X550EM_A_1G_T: case IXGBE_DEV_ID_X550EM_A_1G_T_L: phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; -- 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha @ 2017-12-21 3:23 ` Zhang, Helin 2018-01-10 3:17 ` Zhang, Helin 1 sibling, 0 replies; 10+ messages in thread From: Zhang, Helin @ 2017-12-21 3:23 UTC (permalink / raw) To: Shweta Choudaha, dev; +Cc: Shweta Choudaha, Wang, Liang-min, Tantilov, Emil S > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > Sent: Monday, November 6, 2017 10:25 PM > To: dev@dpdk.org > Cc: Shweta Choudaha > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support > > From: Shweta Choudaha <shweta.choudaha@att.com> > > Initialize MDIO read/write functions for backplan port > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO > > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> > Reviewed-by: Chas Williams <chas3@att.com> > Reviewed-by: Luca Boccassi <bluca@debian.org> > --- > drivers/net/ixgbe/base/ixgbe_x550.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > b/drivers/net/ixgbe/base/ixgbe_x550.c > index 9862391..3f89dc4 100644 > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw > *hw) > } > > switch (hw->device_id) { > + case IXGBE_DEV_ID_X550EM_A_KR_L: Basically the source files in 'base' folder is handled by Intel, I will check if this code change is acceptable by some internal stakeholders. I will let you know later. Thanks, Helin > case IXGBE_DEV_ID_X550EM_A_1G_T: > case IXGBE_DEV_ID_X550EM_A_1G_T_L: > phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; > -- > 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha 2017-12-21 3:23 ` Zhang, Helin @ 2018-01-10 3:17 ` Zhang, Helin 2018-01-23 14:14 ` Shweta Choudaha 1 sibling, 1 reply; 10+ messages in thread From: Zhang, Helin @ 2018-01-10 3:17 UTC (permalink / raw) To: Shweta Choudaha, dev, Kirsher, Jeffrey T, Greenwalt, Paul, Tantilov, Emil S, Nguyen, Anthony L Cc: Shweta Choudaha, Lu, Wenzhuo, Ananyev, Konstantin, Dai, Wei, Wu, Jingjing, Zhang, Qi Z > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > Sent: Monday, November 6, 2017 10:25 PM > To: dev@dpdk.org > Cc: Shweta Choudaha > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support > > From: Shweta Choudaha <shweta.choudaha@att.com> > > Initialize MDIO read/write functions for backplan port > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO > > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> > Reviewed-by: Chas Williams <chas3@att.com> > Reviewed-by: Luca Boccassi <bluca@debian.org> > --- > drivers/net/ixgbe/base/ixgbe_x550.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > b/drivers/net/ixgbe/base/ixgbe_x550.c > index 9862391..3f89dc4 100644 > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw > *hw) > } > > switch (hw->device_id) { > + case IXGBE_DEV_ID_X550EM_A_KR_L: Basically this device ID is for a specific SoC platform, there is no external PHY for it. We prefer to NACK it. I added more experts here to answer more questions if you have. Note that they are not working on DPDK, and they are experts on ixgbe NIC/SW. Or we can discuss more if you have any requests to Intel. Sorry, Helin > case IXGBE_DEV_ID_X550EM_A_1G_T: > case IXGBE_DEV_ID_X550EM_A_1G_T_L: > phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; > -- > 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support 2018-01-10 3:17 ` Zhang, Helin @ 2018-01-23 14:14 ` Shweta Choudaha 0 siblings, 0 replies; 10+ messages in thread From: Shweta Choudaha @ 2018-01-23 14:14 UTC (permalink / raw) To: Zhang, Helin Cc: dev, Kirsher, Jeffrey T, Greenwalt, Paul, Tantilov, Emil S, Nguyen, Anthony L, Shweta Choudaha, Lu, Wenzhuo, Ananyev, Konstantin, Dai, Wei, Wu, Jingjing, Zhang, Qi Z Hi Helin, Thanks for the review. Yes , the backplane interfaces(x550em) does not have a phy connected but it still MDIO lines for control. The requirement for us is to be able to access phy registers over backplane MDIO . I 've an updated patchset which is cleaner. I 'll send that for review. Thanks, Shweta On Wed, Jan 10, 2018 at 3:17 AM, Zhang, Helin <helin.zhang@intel.com> wrote: > > > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > > Sent: Monday, November 6, 2017 10:25 PM > > To: dev@dpdk.org > > Cc: Shweta Choudaha > > Subject: [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO > support > > > > From: Shweta Choudaha <shweta.choudaha@att.com> > > > > Initialize MDIO read/write functions for backplan port > > (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO > > > > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> > > Reviewed-by: Chas Williams <chas3@att.com> > > Reviewed-by: Luca Boccassi <bluca@debian.org> > > --- > > drivers/net/ixgbe/base/ixgbe_x550.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > > b/drivers/net/ixgbe/base/ixgbe_x550.c > > index 9862391..3f89dc4 100644 > > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > > @@ -2374,6 +2374,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw > > *hw) > > } > > > > switch (hw->device_id) { > > + case IXGBE_DEV_ID_X550EM_A_KR_L: > Basically this device ID is for a specific SoC platform, there is no > external PHY for it. > We prefer to NACK it. I added more experts here to answer more questions > if you have. > Note that they are not working on DPDK, and they are experts on ixgbe > NIC/SW. > Or we can discuss more if you have any requests to Intel. > > Sorry, > Helin > > > case IXGBE_DEV_ID_X550EM_A_1G_T: > > case IXGBE_DEV_ID_X550EM_A_1G_T_L: > > phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; > > -- > > 2.1.4 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 " Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha @ 2017-12-21 3:25 ` Zhang, Helin 2018-01-23 15:12 ` Shweta Choudaha 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 " Shweta Choudaha 2 siblings, 1 reply; 10+ messages in thread From: Zhang, Helin @ 2017-12-21 3:25 UTC (permalink / raw) To: Shweta Choudaha, dev; +Cc: Shweta Choudaha In general, I'd suggest to add two things together with this patch set. 1. test cases in testpmd. 2. documentation in release notes, testpmd doc, and others if needed. Regards, Helin > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > Sent: Monday, November 6, 2017 10:25 PM > To: dev@dpdk.org > Cc: Shweta Choudaha > Subject: [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs > > From: Shweta Choudaha <shweta.choudaha@att.com> > > Add ixgbe MDIO access APIs to read and write PHY registers when being used > as a backplane port. Export these APIs via the map file > > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> > Reviewed-by: Chas Williams <chas3@att.com> > Reviewed-by: Luca Boccassi <bluca@debian.org> > --- > drivers/net/ixgbe/rte_pmd_ixgbe.c | 53 > +++++++++++++++++++++++++++++ > drivers/net/ixgbe/rte_pmd_ixgbe.h | 39 +++++++++++++++++++++ > drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 7 ++++ > 3 files changed, 99 insertions(+) > > diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c > b/drivers/net/ixgbe/rte_pmd_ixgbe.c > index f127378..34d8cb4 100644 > --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c > @@ -1041,3 +1041,56 @@ rte_pmd_ixgbe_bypass_wd_reset(uint16_t > port_id) > return ixgbe_bypass_wd_reset(dev); > } > #endif > + > +static void rte_pmd_ixgbe_get_hw_phy(uint16_t port, struct ixgbe_hw > **hw, > + struct ixgbe_phy_info **phy) > +{ > + struct rte_eth_dev *dev; > + > + *hw = NULL; > + *phy = NULL; > + > + dev = &rte_eth_devices[port]; > + if (!is_ixgbe_supported(dev)) > + return; > + > + *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + if (!*hw) > + return; > + > + *phy = &(*hw)->phy; > +} > + > +int > +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, > + uint32_t dev_type, uint16_t *phy_data) { > + struct ixgbe_hw *hw; > + struct ixgbe_phy_info *phy; > + > + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); > + > + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); > + > + if (!hw || !phy) > + return -ENOTSUP; > + > + return phy->ops.read_reg_mdi(hw, reg_addr, dev_type, phy_data); } > + > +int > +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, > + uint32_t dev_type, uint16_t phy_data) { > + struct ixgbe_hw *hw; > + struct ixgbe_phy_info *phy; > + > + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); > + > + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); > + > + if (!hw || !phy) > + return -ENOTSUP; > + > + return phy->ops.write_reg_mdi(hw, reg_addr, dev_type, phy_data); } > diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h > b/drivers/net/ixgbe/rte_pmd_ixgbe.h > index 81b18f8..5d36f8a 100644 > --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h > @@ -601,6 +601,45 @@ int > rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t > *wd_timeout); > */ > int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port); > > +/** > + * Read PHY register using MDIO > + * > + * @param port > + * The port identifier of the Ethernet device. > + * @param reg_addr > + * 32 bit PHY Register > + * @param dev_type > + * Always Unused > + * @param phy_data > + * Pointer for reading PHY register data > + * @return > + * - (0) if successful. > + * - (-ENOTSUP) if hardware doesn't support. > + * - (-ENODEV) if *port* invalid. > + */ > +int > +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, > + uint32_t dev_type, uint16_t *phy_data); > + > +/** > + * Write data to PHY register using MDIO > + * > + * @param port > + * The port identifier of the Ethernet device. > + * @param reg_addr > + * 32 bit PHY Register > + * @param dev_type > + * Always unused > + * @param phy_data > + * Data to write to PHY register > + * @return > + * - (0) if successful. > + * - (-ENOTSUP) if hardware doesn't support. > + * - (-ENODEV) if *port* invalid. > + */ > +int > +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, > + uint32_t dev_type, uint16_t phy_data); > > /** > * Response sent back to ixgbe driver from user app after callback diff --git > a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > index bf77674..ce72c73 100644 > --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > @@ -52,3 +52,10 @@ DPDK_17.08 { > rte_pmd_ixgbe_bypass_wd_timeout_show; > rte_pmd_ixgbe_bypass_wd_timeout_store; > } DPDK_17.05; > + > +EXPERIMENTAL { > + global: > + > + rte_pmd_ixgbe_mdio_read; > + rte_pmd_ixgbe_mdio_write; > +} DPDK_17.08; > -- > 2.1.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs 2017-12-21 3:25 ` [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs Zhang, Helin @ 2018-01-23 15:12 ` Shweta Choudaha 0 siblings, 0 replies; 10+ messages in thread From: Shweta Choudaha @ 2018-01-23 15:12 UTC (permalink / raw) To: Zhang, Helin; +Cc: dev, Shweta Choudaha Hi Helin, Thanks for the review. I 'll look at adding test cases too. In the meantime, updated this patch to reflect changes in patch 2 of the series. Thanks, Shweta On Thu, Dec 21, 2017 at 3:25 AM, Zhang, Helin <helin.zhang@intel.com> wrote: > In general, I'd suggest to add two things together with this patch set. > 1. test cases in testpmd. > 2. documentation in release notes, testpmd doc, and others if needed. > > Regards, > Helin > > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shweta Choudaha > > Sent: Monday, November 6, 2017 10:25 PM > > To: dev@dpdk.org > > Cc: Shweta Choudaha > > Subject: [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs > > > > From: Shweta Choudaha <shweta.choudaha@att.com> > > > > Add ixgbe MDIO access APIs to read and write PHY registers when being > used > > as a backplane port. Export these APIs via the map file > > > > Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> > > Reviewed-by: Chas Williams <chas3@att.com> > > Reviewed-by: Luca Boccassi <bluca@debian.org> > > --- > > drivers/net/ixgbe/rte_pmd_ixgbe.c | 53 > > +++++++++++++++++++++++++++++ > > drivers/net/ixgbe/rte_pmd_ixgbe.h | 39 +++++++++++++++++++++ > > drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 7 ++++ > > 3 files changed, 99 insertions(+) > > > > diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c > > b/drivers/net/ixgbe/rte_pmd_ixgbe.c > > index f127378..34d8cb4 100644 > > --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c > > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c > > @@ -1041,3 +1041,56 @@ rte_pmd_ixgbe_bypass_wd_reset(uint16_t > > port_id) > > return ixgbe_bypass_wd_reset(dev); > > } > > #endif > > + > > +static void rte_pmd_ixgbe_get_hw_phy(uint16_t port, struct ixgbe_hw > > **hw, > > + struct ixgbe_phy_info **phy) > > +{ > > + struct rte_eth_dev *dev; > > + > > + *hw = NULL; > > + *phy = NULL; > > + > > + dev = &rte_eth_devices[port]; > > + if (!is_ixgbe_supported(dev)) > > + return; > > + > > + *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + if (!*hw) > > + return; > > + > > + *phy = &(*hw)->phy; > > +} > > + > > +int > > +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, > > + uint32_t dev_type, uint16_t *phy_data) { > > + struct ixgbe_hw *hw; > > + struct ixgbe_phy_info *phy; > > + > > + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); > > + > > + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); > > + > > + if (!hw || !phy) > > + return -ENOTSUP; > > + > > + return phy->ops.read_reg_mdi(hw, reg_addr, dev_type, phy_data); } > > + > > +int > > +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, > > + uint32_t dev_type, uint16_t phy_data) { > > + struct ixgbe_hw *hw; > > + struct ixgbe_phy_info *phy; > > + > > + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); > > + > > + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); > > + > > + if (!hw || !phy) > > + return -ENOTSUP; > > + > > + return phy->ops.write_reg_mdi(hw, reg_addr, dev_type, phy_data); } > > diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h > > b/drivers/net/ixgbe/rte_pmd_ixgbe.h > > index 81b18f8..5d36f8a 100644 > > --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h > > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h > > @@ -601,6 +601,45 @@ int > > rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t > > *wd_timeout); > > */ > > int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port); > > > > +/** > > + * Read PHY register using MDIO > > + * > > + * @param port > > + * The port identifier of the Ethernet device. > > + * @param reg_addr > > + * 32 bit PHY Register > > + * @param dev_type > > + * Always Unused > > + * @param phy_data > > + * Pointer for reading PHY register data > > + * @return > > + * - (0) if successful. > > + * - (-ENOTSUP) if hardware doesn't support. > > + * - (-ENODEV) if *port* invalid. > > + */ > > +int > > +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, > > + uint32_t dev_type, uint16_t *phy_data); > > + > > +/** > > + * Write data to PHY register using MDIO > > + * > > + * @param port > > + * The port identifier of the Ethernet device. > > + * @param reg_addr > > + * 32 bit PHY Register > > + * @param dev_type > > + * Always unused > > + * @param phy_data > > + * Data to write to PHY register > > + * @return > > + * - (0) if successful. > > + * - (-ENOTSUP) if hardware doesn't support. > > + * - (-ENODEV) if *port* invalid. > > + */ > > +int > > +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, > > + uint32_t dev_type, uint16_t phy_data); > > > > /** > > * Response sent back to ixgbe driver from user app after callback diff > --git > > a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > > b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > > index bf77674..ce72c73 100644 > > --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map > > @@ -52,3 +52,10 @@ DPDK_17.08 { > > rte_pmd_ixgbe_bypass_wd_timeout_show; > > rte_pmd_ixgbe_bypass_wd_timeout_store; > > } DPDK_17.05; > > + > > +EXPERIMENTAL { > > + global: > > + > > + rte_pmd_ixgbe_mdio_read; > > + rte_pmd_ixgbe_mdio_write; > > +} DPDK_17.08; > > -- > > 2.1.4 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [dpdk-dev] [PATCH v3 1/2] net/ixgbe: add and export MDIO APIs 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 " Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha 2017-12-21 3:25 ` [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs Zhang, Helin @ 2018-01-23 15:05 ` Shweta Choudaha 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha 2 siblings, 1 reply; 10+ messages in thread From: Shweta Choudaha @ 2018-01-23 15:05 UTC (permalink / raw) To: dev; +Cc: Shweta Choudaha From: Shweta Choudaha <shweta.choudaha@att.com> Add ixgbe MDIO access APIs to read and write PHY registers when being used as a backplane port. Export these APIs via the map file Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> Reviewed-by: Chas Williams <chas3@att.com> Reviewed-by: Luca Boccassi <bluca@debian.org> --- drivers/net/ixgbe/rte_pmd_ixgbe.c | 53 +++++++++++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe.h | 39 +++++++++++++++++++++ drivers/net/ixgbe/rte_pmd_ixgbe_version.map | 2 ++ 3 files changed, 94 insertions(+) diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c index 001a8647e..a3f376e11 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c @@ -1012,3 +1012,56 @@ rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id) return ixgbe_bypass_wd_reset(dev); } #endif + +static void rte_pmd_ixgbe_get_hw_phy(uint16_t port, struct ixgbe_hw **hw, + struct ixgbe_phy_info **phy) +{ + struct rte_eth_dev *dev; + + *hw = NULL; + *phy = NULL; + + dev = &rte_eth_devices[port]; + if (!is_ixgbe_supported(dev)) + return; + + *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (!*hw) + return; + + *phy = &(*hw)->phy; +} + +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.read_reg(hw, reg_addr, dev_type, phy_data); +} + +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data) +{ + struct ixgbe_hw *hw; + struct ixgbe_phy_info *phy; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + rte_pmd_ixgbe_get_hw_phy(port, &hw, &phy); + + if (!hw || !phy) + return -ENOTSUP; + + return phy->ops.write_reg(hw, reg_addr, dev_type, phy_data); +} diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.h b/drivers/net/ixgbe/rte_pmd_ixgbe.h index 463a78e50..1fd6280e5 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe.h +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.h @@ -573,6 +573,45 @@ int rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t *wd_timeout); */ int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port); +/** + * Read PHY register using MDIO with swfw semaphore lock + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always Unused + * @param phy_data + * Pointer for reading PHY register data + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_read(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t *phy_data); + +/** + * Write data to PHY register using MDIO with swfw semaphore lock + * + * @param port + * The port identifier of the Ethernet device. + * @param reg_addr + * 32 bit PHY Register + * @param dev_type + * Always unused + * @param phy_data + * Data to write to PHY register + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + * - (-ENODEV) if *port* invalid. + */ +int +rte_pmd_ixgbe_mdio_write(uint16_t port, uint32_t reg_addr, + uint32_t dev_type, uint16_t phy_data); /** * Response sent back to ixgbe driver from user app after callback diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map index bf776742c..9cad217e9 100644 --- a/drivers/net/ixgbe/rte_pmd_ixgbe_version.map +++ b/drivers/net/ixgbe/rte_pmd_ixgbe_version.map @@ -51,4 +51,6 @@ DPDK_17.08 { rte_pmd_ixgbe_bypass_wd_reset; rte_pmd_ixgbe_bypass_wd_timeout_show; rte_pmd_ixgbe_bypass_wd_timeout_store; + rte_pmd_ixgbe_mdio_read; + rte_pmd_ixgbe_mdio_write; } DPDK_17.05; -- 2.11.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [dpdk-dev] [PATCH v3 2/2] net/ixgbe : backplane port MDIO support 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 " Shweta Choudaha @ 2018-01-23 15:05 ` Shweta Choudaha 0 siblings, 0 replies; 10+ messages in thread From: Shweta Choudaha @ 2018-01-23 15:05 UTC (permalink / raw) To: dev; +Cc: Shweta Choudaha From: Shweta Choudaha <shweta.choudaha@att.com> Initialize and implement MDIO read/write functions for backplane port (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com> Reviewed-by: Chas Williams <chas3@att.com> Reviewed-by: Luca Boccassi <bluca@debian.org> --- drivers/net/ixgbe/base/ixgbe_x550.c | 54 ++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index f7401c060..885eaccfe 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -613,18 +613,62 @@ s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); } +/** + * ixgbe_read_phy_reg_x550em - Reads specified PHY register + * @hw: pointer to hardware structure + * @reg_addr: 32 bit address of PHY register to read + * @device_type: 5 bit device type + * @phy_data: Pointer to read data from PHY register + * + * Reads a value from a specified PHY register using the SWFW lock and PHY + * Token. The PHY Token is needed since the MDIO can be shared between MAC + * instances. + **/ STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { - UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); - return IXGBE_NOT_IMPLEMENTED; + s32 status; + u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; + + DEBUGFUNC("ixgbe_read_phy_reg_x550em"); + + if (hw->mac.ops.acquire_swfw_sync(hw, mask)) + return IXGBE_ERR_SWFW_SYNC; + + status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); + + hw->mac.ops.release_swfw_sync(hw, mask); + + return status; } +/** + * ixgbe_write_phy_reg_x550em- Writes specified PHY register + * @hw: pointer to hardware structure + * @reg_addr: 32 bit PHY register to write + * @device_type: 5 bit device type + * @phy_data: Data to write to the PHY register + * + * Writes a value to specified PHY register using the SWFW lock and PHY Token. + * The PHY Token is needed since the MDIO can be shared between MAC instances. + **/ STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { - UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); - return IXGBE_NOT_IMPLEMENTED; + s32 status; + u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; + + DEBUGFUNC("ixgbe_write_phy_reg_x550em"); + + if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { + status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, + phy_data); + hw->mac.ops.release_swfw_sync(hw, mask); + } else { + status = IXGBE_ERR_SWFW_SYNC; + } + + return status; } /** @@ -2423,6 +2467,8 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_x550em_kr: + phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; + phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; phy->ops.setup_link = ixgbe_setup_kr_x550em; phy->ops.read_reg = ixgbe_read_phy_reg_x550em; phy->ops.write_reg = ixgbe_write_phy_reg_x550em; -- 2.11.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-01-23 15:12 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-11-06 13:42 [dpdk-dev] [PATCH 1/2] net/ixgbe: add and export MDIO APIs Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 " Shweta Choudaha 2017-11-06 14:25 ` [dpdk-dev] [PATCH v2 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha 2017-12-21 3:23 ` Zhang, Helin 2018-01-10 3:17 ` Zhang, Helin 2018-01-23 14:14 ` Shweta Choudaha 2017-12-21 3:25 ` [dpdk-dev] [PATCH v2 1/2] net/ixgbe: add and export MDIO APIs Zhang, Helin 2018-01-23 15:12 ` Shweta Choudaha 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 " Shweta Choudaha 2018-01-23 15:05 ` [dpdk-dev] [PATCH v3 2/2] net/ixgbe : backplane port MDIO support Shweta Choudaha
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