From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f45.google.com (mail-pa0-f45.google.com [209.85.220.45]) by dpdk.org (Postfix) with ESMTP id 668295955 for ; Mon, 14 Dec 2015 17:29:49 +0100 (CET) Received: by pabur14 with SMTP id ur14so106519198pab.0 for ; Mon, 14 Dec 2015 08:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=3u9vjw9vbUkbpB66ydSRs3VMuhEeI5L4IH/jbKh1yxk=; b=D7U7YlHDFBjbs4MWBkC8pgtRmfYTnQK2BjcK7FgpX2f+ozS/JmMSejRQ4VOvuOAOL+ oWOXtIJDKabtLYPCema1pc+yNTb8GQPaPtro+9hJAGpS3ZuX+mRkA/R5tyi3mAOGB8bE S05dSEb+s73NczZwWYanTkSGAP2RFZCsP0HGPvkDtNXvAxpGxKHm5fJAbZYD2yQ50G79 82zeHfXTH3PPatkqWBJXLJN+tMEOAe5vFnqISy3DniKEBEkVgC/HczLxa+ePze4TrK7z zv4yP1y7HusJwLp7Sifzk34UZLsAhbnDsHZfLOhmrPnNnCVaHZndfB7AQtwBf6an65WX 83Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=3u9vjw9vbUkbpB66ydSRs3VMuhEeI5L4IH/jbKh1yxk=; b=KNvhgaRb+DRZDWR/vS8EXP3J2nEpiUbqv9fUPgyfs3G7kiVijdPYc0HwTT5oYr4qIk 9KnPBQ2MvnTy/zi4JBjLihGX/44+Xf6TFGyB42hVV+WVkQqVXSz8/YglUiEL6AbAffab w33k8f8CVHMTVGm29i4YuzyBY+tuawPGUYrMaHvrXvIDkXef7K7Mmt98xHwum8LSAXu3 HAoBaLtlpLEtDGie4i8TfeQ+jcxsxxLOoqvub160M9WTSKekATDLYkxLgN/5N/Ksl5Z0 2FKefcV/hdbphS6IET7yKuheead6hmQGLWD+avXXCKAZIVcsdn+QVIhKZWESUnWwtxop 4Mlw== X-Gm-Message-State: ALoCoQncqQ9yWtMzn4n4df1x3b7X9rtqPSACAHNF2uD85JWjOrAlcLp3R88QXMMMls/CbH63ei0ziEwFUv7ZIk1t8dwHizXgufMcwd48yaflSqBnmi1vab4= MIME-Version: 1.0 X-Received: by 10.66.227.129 with SMTP id sa1mr47148492pac.132.1450110588542; Mon, 14 Dec 2015 08:29:48 -0800 (PST) Received: by 10.66.13.233 with HTTP; Mon, 14 Dec 2015 08:29:48 -0800 (PST) In-Reply-To: <20151214142508.GA30309@localhost.localdomain> References: <1450098032-21198-1-git-send-email-sshukla@mvista.com> <1450098032-21198-4-git-send-email-sshukla@mvista.com> <20151214142508.GA30309@localhost.localdomain> Date: Mon, 14 Dec 2015 21:59:48 +0530 Message-ID: From: Santosh Shukla To: Jerin Jacob Content-Type: text/plain; charset=UTF-8 Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [ [PATCH v2] 03/13] rte_io: armv7/v8: Introduce api to emulate x86-style of PCI/ISA ioport access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Dec 2015 16:29:50 -0000 On Mon, Dec 14, 2015 at 7:55 PM, Jerin Jacob wrote: > On Mon, Dec 14, 2015 at 06:30:22PM +0530, Santosh Shukla wrote: >> Introducing rte_io.h header file to emulate x86-style of ioport rd/wr api >> example {in,out}[bwl] and {in_p,out_p}[bwl]. Api support added for armv7 and >> armv8 both. >> >> Current use-case for this api is for virtio_pci module that does x86-style >> rd/wr. >> >> Tested for armv8/ThunderX platform and build successfully for armv7. >> >> Signed-off-by: Santosh Shukla >> --- >> lib/librte_eal/common/Makefile | 1 + >> lib/librte_eal/common/include/arch/arm/rte_io.h | 60 ++++++++ >> lib/librte_eal/common/include/arch/arm/rte_io_32.h | 155 ++++++++++++++++++++ >> lib/librte_eal/common/include/arch/arm/rte_io_64.h | 155 ++++++++++++++++++++ >> lib/librte_eal/common/include/generic/rte_io.h | 81 ++++++++++ >> 5 files changed, 452 insertions(+) >> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io.h >> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_32.h >> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_64.h >> create mode 100644 lib/librte_eal/common/include/generic/rte_io.h >> >> diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile >> index f5ea0ee..1021e1d 100644 >> --- a/lib/librte_eal/common/Makefile >> +++ b/lib/librte_eal/common/Makefile >> @@ -48,6 +48,7 @@ endif >> >> GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h >> GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h >> +GENERIC_INC += rte_io.h >> # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk >> ARCH_DIR ?= $(RTE_ARCH) >> ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h)) >> diff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h >> new file mode 100644 >> index 0000000..b4f1613 >> --- /dev/null >> +++ b/lib/librte_eal/common/include/arch/arm/rte_io.h >> @@ -0,0 +1,60 @@ >> +/* >> + * BSD LICENSE >> + * >> + * Copyright(c) 2015 Cavium Networks. All rights reserved. >> + * All rights reserved. >> + * >> + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. >> + * All rights reserved. >> + * >> + * ARM helper api to emulate x86-style of {in , out}[bwl] api used for >> + * accessing PCI/ISA IO address space. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions >> + * are met: >> + * >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in >> + * the documentation and/or other materials provided with the >> + * distribution. >> + * * Neither the name of Intel Corporation nor the names of its >> + * contributors may be used to endorse or promote products derived >> + * from this software without specific prior written permission. >> + * >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +#ifndef _RTE_IO_ARM_H_ >> +#define _RTE_IO_ARM_H_ >> + >> +/* >> + * @File >> + * Use-case: >> + * Currently virtio pci does IO access in x86-way i.e. IO_RESOURCE_IO way, It >> + * access the pci address space by port_number. The ARM doesn't have >> + * instructions for direct IO access. In ARM: IO's are memory mapped. >> + * >> + * Below helper api allow virtio_pci pmd driver to access IO's for arm/arm64 >> + * arch in x86-style of apis example: {in , out}[bwl] and {in_p , out_p}[bwl]. >> + */ >> + >> +#ifdef RTE_ARCH_64 >> +#include >> +#else >> +#include >> +#endif >> + >> +#endif /* _RTE_IO_ARM_H_ */ >> diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_32.h b/lib/librte_eal/common/include/arch/arm/rte_io_32.h >> new file mode 100644 >> index 0000000..0e79427 >> --- /dev/null >> +++ b/lib/librte_eal/common/include/arch/arm/rte_io_32.h >> @@ -0,0 +1,155 @@ >> +/* >> + * BSD LICENSE >> + * >> + * Copyright(c) 2015 Cavium Networks. All rights reserved. >> + * All rights reserved. >> + * >> + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. >> + * All rights reserved. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions >> + * are met: >> + * >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in >> + * the documentation and/or other materials provided with the >> + * distribution. >> + * * Neither the name of Intel Corporation nor the names of its >> + * contributors may be used to endorse or promote products derived >> + * from this software without specific prior written permission. >> + * >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +#ifndef _RTE_IO_ARM32_H_ >> +#define _RTE_IO_ARM32_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_io.h" >> + >> +/* >> + * Generic IO read/write api for arm: Refer TRM >> + */ >> +static inline void raw_writeb(uint8_t val, uint32_t addr) >> +{ > > armv7 and armv8 instructions looks same for both raw_* implementation. > The difference in length of "addr" can be abstracted as uintptr_t to > reuse the code. > > Use AT&T sytax on inline assembly as mentioned in > doc/guides/contributing/coding_style.rst > > Inline ASM in C code > ~~~~~~~~~~~~~~~~~~~~ > > The ``asm`` and ``volatile`` keywords do not have underscores. The AT&T > syntax should be used. > Input and output operands should be named to avoid confusion, as shown > in the following example: > > .. code-block:: c > > asm volatile("outb %[val], %[port]" > : : > [port] "dN" (port), > [val] "a" (val)); > > Ok. >> + asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline void raw_writew(uint16_t val, uint32_t addr) >> +{ >> + asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline void raw_writel(uint32_t val, uint32_t addr) >> +{ >> + asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline uint8_t raw_readb(uint32_t addr) >> +{ >> + uint8_t val; >> + asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +static inline uint16_t raw_readw(uint32_t addr) >> +{ >> + uint16_t val; >> + asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +static inline uint32_t raw_readl(uint32_t addr) >> +{ >> + uint32_t val; >> + asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +/** >> + * Emulate x86-style of ioport api implementation for arm/arm64. Included API >> + * - {in, out}{b, w, l}() >> + * - {in_p, out_p} {b, w, l} () >> + */ >> + >> +static inline uint8_t inb(unsigned long addr) >> +{ >> + return raw_readb(addr); >> +} >> + >> +static inline uint16_t inw(unsigned long addr) >> +{ >> + return raw_readw(addr); >> +} >> + >> +static inline uint32_t inl(unsigned long addr) >> +{ >> + return raw_readl(addr); >> +} >> + >> +static inline void outb(uint8_t value, unsigned long addr) >> +{ >> + raw_writeb(value, addr); >> +} >> + >> +static inline void outw(uint16_t value, unsigned long addr) >> +{ >> + raw_writew(value, addr); >> +} >> + >> +static inline void outl(uint32_t value, unsigned long addr) >> +{ >> + raw_writel(value, addr); >> +} >> + >> +static inline uint8_t inb_p(unsigned long addr) >> +{ >> + return inb(addr); >> +} >> + >> +static inline uint16_t inw_p(unsigned long addr) >> +{ >> + return inw(addr); >> +} >> + >> +static inline uint32_t inl_p(unsigned long addr) >> +{ >> + return inl(addr); >> +} >> + >> +static inline void outb_p(uint8_t value, unsigned long addr) >> +{ >> + outb(value, addr); >> +} >> + >> +static inline void outw_p(uint16_t value, unsigned long addr) >> +{ >> + outw(value, addr); >> +} >> + >> +static inline void outl_p(uint32_t value, unsigned long addr) >> +{ >> + outl(value, addr); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_IO_ARM32_H_ */ >> diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_64.h b/lib/librte_eal/common/include/arch/arm/rte_io_64.h >> new file mode 100644 >> index 0000000..b601f2a >> --- /dev/null >> +++ b/lib/librte_eal/common/include/arch/arm/rte_io_64.h >> @@ -0,0 +1,155 @@ >> +/* >> + * BSD LICENSE >> + * >> + * Copyright(c) 2015 Cavium Networks. All rights reserved. >> + * All rights reserved. >> + * >> + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. >> + * All rights reserved. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions >> + * are met: >> + * >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in >> + * the documentation and/or other materials provided with the >> + * distribution. >> + * * Neither the name of Intel Corporation nor the names of its >> + * contributors may be used to endorse or promote products derived >> + * from this software without specific prior written permission. >> + * >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +#ifndef _RTE_IO_ARM64_H_ >> +#define _RTE_IO_ARM64_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_io.h" >> + >> +/* >> + * Generic IO read/write api for arm64: Refer TRM >> + */ >> +static inline void raw_writeb(uint8_t val, uint64_t addr) >> +{ >> + asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline void raw_writew(uint16_t val, uint64_t addr) >> +{ >> + asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline void raw_writel(uint32_t val, uint64_t addr) >> +{ >> + asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); >> +} >> + >> +static inline uint8_t raw_readb(uint64_t addr) >> +{ >> + uint8_t val; >> + asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +static inline uint16_t raw_readw(uint64_t addr) >> +{ >> + uint16_t val; >> + asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +static inline uint32_t raw_readl(uint64_t addr) >> +{ >> + uint32_t val; >> + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); >> + return val; >> +} >> + >> +/** >> + * Emulate x86-style of ioport api implementation for arm/arm64. Included API >> + * - {in, out}{b, w, l}() >> + * - {in_p, out_p} {b, w, l} () >> + */ >> + >> +static inline uint8_t inb(unsigned long addr) >> +{ >> + return raw_readb(addr); >> +} >> + >> +static inline uint16_t inw(unsigned long addr) >> +{ >> + return raw_readw(addr); >> +} >> + >> +static inline uint32_t inl(unsigned long addr) >> +{ >> + return raw_readl(addr); >> +} >> + >> +static inline void outb(uint8_t value, unsigned long addr) >> +{ >> + raw_writeb(value, addr); >> +} >> + >> +static inline void outw(uint16_t value, unsigned long addr) >> +{ >> + raw_writew(value, addr); >> +} >> + >> +static inline void outl(uint32_t value, unsigned long addr) >> +{ >> + raw_writel(value, addr); >> +} >> + >> +static inline uint8_t inb_p(unsigned long addr) >> +{ >> + return inb(addr); >> +} >> + >> +static inline uint16_t inw_p(unsigned long addr) >> +{ >> + return inw(addr); >> +} >> + >> +static inline uint32_t inl_p(unsigned long addr) >> +{ >> + return inl(addr); >> +} >> + >> +static inline void outb_p(uint8_t value, unsigned long addr) >> +{ >> + outb(value, addr); >> +} >> + >> +static inline void outw_p(uint16_t value, unsigned long addr) >> +{ >> + outw(value, addr); >> +} >> + >> +static inline void outl_p(uint32_t value, unsigned long addr) >> +{ >> + outl(value, addr); >> +} >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_IO_ARM64_H_ */ >> diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h >> new file mode 100644 >> index 0000000..7cc4279 >> --- /dev/null >> +++ b/lib/librte_eal/common/include/generic/rte_io.h >> @@ -0,0 +1,81 @@ >> +/* >> + * BSD LICENSE >> + * >> + * Copyright(c) 2015 Cavium Networks. All rights reserved. >> + * All rights reserved. >> + * >> + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. >> + * All rights reserved. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions >> + * are met: >> + * >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in >> + * the documentation and/or other materials provided with the >> + * distribution. >> + * * Neither the name of Intel Corporation nor the names of its >> + * contributors may be used to endorse or promote products derived >> + * from this software without specific prior written permission. >> + * >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> + */ >> + >> +#ifndef _RTE_IO_H_ >> +#define _RTE_IO_H_ >> + >> +/** >> + * @file >> + * >> + * IO operations. >> + * >> + * This file defines an API for IO rd/wr inline-functions, API's of the style >> + * {in , out}[bwl] and {in_p, out_p} [bwl]. which are architecture-dependent. >> + * Used by non-x86 archs. In particular used by arm/arm64 arch. >> + */ >> + >> +#include >> + >> +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) > > Shouldn't be > #if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) || > defined(RTE_ARCH_X86_X32) ? > sys/io.h code incident in dpdk using similar ifdef so used, I guess your are right on including X86_X32 as because it is now include/generic/ direcotry. We'll do in v3. Thanks > >> +#include >> +#else >> + >> +/** >> + * Emulate x86-style of ioport api implementation for arm/arm64. Included API >> + * - {in, out}{b, w, l}() >> + * - {in_p, out_p} {b, w, l} () >> + */ >> + >> +static inline uint8_t inb(unsigned long addr); >> +static inline uint16_t inw(unsigned long addr); >> +static inline uint32_t inl(unsigned long addr); >> + >> +static inline void outb(uint8_t value, unsigned long addr); >> +static inline void outw(uint16_t value, unsigned long addr); >> +static inline void outl(uint32_t value, unsigned long addr); >> + >> +static inline uint8_t inb_p(unsigned long addr); >> +static inline uint16_t inw_p(unsigned long addr); >> +static inline uint32_t inl_p(unsigned long addr); >> + >> +static inline void outb_p(uint8_t value, unsigned long addr); >> +static inline void outw_p(uint16_t value, unsigned long addr); >> +static inline void outl_p(uint32_t value, unsigned long addr); >> + >> +#endif >> + >> +#endif /* _RTE_IO_H_ */ >> + >> -- >> 1.7.9.5 >>