From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by dpdk.org (Postfix) with ESMTP id 398A295CD for ; Tue, 2 Feb 2016 16:51:55 +0100 (CET) Received: by mail-pf0-f179.google.com with SMTP id 65so107192160pfd.2 for ; Tue, 02 Feb 2016 07:51:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=Q7MMh5FcMB24IZCHzpa06VBoOTBudF3Hb+hbiTxG7DU=; b=YtWJSNUxRGNucIR5ZYEvKTWEvPcOlseqXZnKbp/B3TBXvAjew+eUGhBAoCuaOqZsvV STX6bh5aPtZIaIO26oOwP/VfDoFCvhZ4PU2sGXwggSRi7bU16U3C8b4Zp/2WVQgdI5Zl Bk7yXBkKNhxhOaV6M0+CFumh05hc5KmwWmnsLbUxnDB5ITL+C9FSy7SK6wk9lqrnwVcc AnZ9tq1YUtd0m9xohCt00RnWvS/Sxlffh5rlEar/Q2m5ASOaIr/Q02fG+IrTQHpy7a5G dxtztLPTLe/8cAvKzGNsvvcdMlz1gi4NNY+QXASI9tCBe6TOJUBMHOlsbDNpMRNSZPrp dX7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=Q7MMh5FcMB24IZCHzpa06VBoOTBudF3Hb+hbiTxG7DU=; b=USrMljDPwUi5N9QWHHwODYNbZ2bSBGvCKi2j4ln1iZmXlUqMTMLEj8lVshm0GpjAbE NE8gAnAQSxBUYOKTCRwzC1RFodW56sATd/fnR7HHTkVqSfTYQY53aH7eCecq0PPHRgDv oo/8P4EaE/t0X1kDiYuz2wrcxahyoR9kAGESnSC1zugHR7wQT7Ajpcty1gAsXUOWH/Gt UpJS/xHCTb5FlrdOIpMVd7OWmX+cNDYkGZWlaIYQ5FUmwMF/SOrIEoLZkOdshQlVHu3y xfGoi9vk2tWzFDCJKJcQmViyLgrFfeBjfxFIcSwlOH8WzZ5urFepYXIhzyQXF0ghmmhb nv8g== X-Gm-Message-State: AG10YOTTFDUW1iOMje2+MJTYYnA+W9rDCqU9cVtScm1budYDZD6TRhOhZTimeq28jqtjQzDz9il78WM2ji6bs/+Q MIME-Version: 1.0 X-Received: by 10.98.14.69 with SMTP id w66mr48336631pfi.144.1454428314609; Tue, 02 Feb 2016 07:51:54 -0800 (PST) Received: by 10.66.12.132 with HTTP; Tue, 2 Feb 2016 07:51:54 -0800 (PST) In-Reply-To: <20160202084933.GJ4257@yliu-dev.sh.intel.com> References: <1454091717-32251-1-git-send-email-sshukla@mvista.com> <20160201134854.GE4257@yliu-dev.sh.intel.com> <20160202054345.GI4257@yliu-dev.sh.intel.com> <20160202084933.GJ4257@yliu-dev.sh.intel.com> Date: Tue, 2 Feb 2016 21:21:54 +0530 Message-ID: From: Santosh Shukla To: Yuanhan Liu Content-Type: text/plain; charset=UTF-8 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH v6 1/8] eal: pci: add api to rd/wr pci bar region X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Feb 2016 15:51:55 -0000 On Tue, Feb 2, 2016 at 2:19 PM, Yuanhan Liu wrote: > On Tue, Feb 02, 2016 at 06:50:18AM +0100, David Marchand wrote: >> On Tue, Feb 2, 2016 at 6:43 AM, Yuanhan Liu wrote: >> > On Tue, Feb 02, 2016 at 09:44:14AM +0530, Santosh Shukla wrote: >> >> Current use-case is virtio: It is used as io_bar which is first >> >> bar[1]. But implementation is generic, can be used to do rd/wr for >> >> other bar index too. Also vfio facilitate user to do rd/wr to pci_bars >> >> w/o mapping that bar, So apis will be useful for such cases in future. >> >> >> >> AFAIU: uio has read/write_config api only and Yes if bar region mapped >> >> then no need to do rd/wr, user can directly access the pci_memory. But >> >> use-case of this api entirely different: unmapped memory by >> >> application context i.e.. vfio_rd/wr-way {pread/pwrite-way}. >> >> >> >> Is above explanation convincing? Pl. let me know. >> > >> > TBH, not really. So, as you stated, it should be generic APIs to >> > read/write bar space, but limiting it to VFIO only and claiming >> > that read/write bar space is not support by other drivers (such >> > as UIO) while in fact it can (in some ways) doesn't seem right >> > to me. >> > >> > Anyway, it's just some thoughts from me. David, comments? >> >> >From the very start, same opinion. >> We should have a unique api to access those, and eal should hide >> details like kernel drivers (uio, vfio, whatever) to the pmd. >> >> Now the thing is, how to do this in an elegant and efficient way. > > I was thinking that we may just make it be IO port specific read/ > write functions: > Ok, > rte_eal_pci_ioport_read(dev, bar, buf, size) > { > > return if not an IO bar; > > if (has io) > return inb/w/l(); > In that case, It may be r / if (has io) / if (drv->kdrv == UIO) > if (vfio) > return vfio_ioport_read(); > > else, claim aloud that io port read is not allowed > } > > Let us not handle memory bar resource here: in such case, you should > go with rte_eal_pci_map_device() and do it with memory mapped io. > > Does that make any sense? > I am not entirely sure. Are you considering IGB_UIO, UIO_GENERIC and NIC_UIO: all the cases ? > --yliu